Annotation of sys/arch/alpha/pci/mcpciareg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: mcpciareg.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */
2: /* $NetBSD: mcpciareg.h,v 1.7 2006/05/17 21:32:59 drochner Exp $ */
3:
4: /*
5: * Copyright (c) 1998 by Matthew Jacob
6: * NASA AMES Research Center.
7: * All rights reserved.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice immediately at the beginning of the file, without modification,
14: * this list of conditions, and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25: * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: */
33:
34: /*
35: * Taken from:
36: *
37: * ``RAWHIDE Systems Programmer's Manual, Revision 1.4''
38: */
39:
40: #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
41:
42: /*
43: * There are 4 possible PCI busses per MCBUS.
44: *
45: * (from mcpcia.h, Digital Unix 4.0E):
46: *
47: * I/O Space Per PCI Node (8GBytes per)
48: * ------------------------------------
49: * (8+x)8 0000 0000 - (8+x)9 FFFF FFFF - I/O Space for PCI0
50: * (8+x)A 0000 0000 - (8+x)B FFFF FFFF - I/O Space for PCI1
51: * (8+x)C 0000 0000 - (8+x)D FFFF FFFF - I/O Space for PCI2
52: * (8+x)E 0000 0000 - (8+x)F FFFF FFFF - I/O Space for PCI3
53: *
54: * CPU to PCI Address Mapping:
55: * ---------------------------
56: *
57: * +---+-------+-------+--+--+--+--+--+--+---------------+----------+-----+
58: * | 1 | GID | MID | | | | | | | Byte Aligned | Byte Len | Zero|
59: * | | | | | | | | | | I/O Address | Field | |
60: * +---+-------+-------+--+--+--+--+--+--+---------------+----------+-----+
61: * 39 38 36 35 33 32 31 30 29 28 27 26 5 4 3 2 0
62: *
63: * <39> - I/O Select (Always 1 for direct I/O access)
64: *
65: * <38-36> - Global Bus slot # (MCBUS #)
66: * GID slot #0->7 (MCBUS #0->7)
67: *
68: * <35-33> - MCBUS Slot #
69: * MCBUS slot 0->7
70: *
71: * <32-27> - PCI Address Space
72: * 0.xxxxx = Sparse Memory Space ( 4GB on MCBUS; 128MB on PCI)
73: * 1.0xxxx = Dense Memory Space ( 2GB on MCBUS; 2GB on PCI)
74: * 1.10xxx = Sparse IO Space ( 1GB on MCBUS; 32MB on PCI)
75: * 1.110xx = Sparse Config Space (512MB on MCBUS; 16MB on PCI)
76: * 1.1110x = PCI Bridge CSR Space (256MB on MCBUS) -- Sparse-mapped!
77: * 1.11110 = Interrupt Acknowledge (128MB on MCBUS)
78: * 1.11111 = Unused (128MB on MCBUS)
79: *
80: * ------------------------------------------------------------
81: * CPU to PCI Address Mapping for MCBUS-PCIy Bridge on MCBUS x:
82: * ------------------------------------------------------------
83: *
84: * CPU Address Range PCI Address Range PCI Address Space
85: * ------------------------ --------------------- ------------------------
86: * (8+x)(8+y*2).0000.0000 0000.0000 - 00FF.FFFF PCIy Sparse Memory Space
87: * - (8+x)(8+y*2).1FFF.FFFF (fixed, lower 16MB)
88: *
89: * (8+x)(8+y*2).2000.0000 0100.0000 - 07FF.FFFF PCIy Sparse Memory Space
90: * - (8+x)(8+y*2).FFFF.FFFF (variable, offset = 0)
91: *
92: * (8+x)(9+y*2).0000.0000 0000.0000 - 7FFF.FFFF PCIy Dense Memory Space
93: * - (8+x)(9+y*2).7FFF.FFFF or 8000.0000 - FFFF.FFFF if HAE_DENSE_MEM = 1
94: *
95: * (8+x)(9+y*2).8000.0000 0000.0000 - 0000.FFFF PCIy Sparse IO Space
96: * - (8+x)(9+y*2).801F.FFFF (fixed, lower 64K)
97: *
98: * (8+x)(9+y*2).8020.0000 0001.0000 - 01FF.FFFF PCIy Sparse IO Space
99: * - (8+x)(9+y*2).BFFF.FFFF (variable, offset = 0)
100: *
101: * (8+x)(9+y*2).C000.0000 0000.0000 - 0FFF.FFFF PCIy Config Space (16MB)
102: * - (8+x)(9+y*2).DFFF.FFFF
103: *
104: * (8+x)(9+y*2).E000.0000 N/A PCIy-Bridge CSR Space
105: * (8MB)
106: * - (8+x)(9+y*2).EFFF.FFFF
107: *
108: * (8+x)(9+y*2).F000.0000 N/A Unused
109: * - (8+x)(9+y*2).F000.3EFF
110: *
111: * (8+x)(9+y*2).F000.3F00, N/A PCIy Interrupt ACK0
112: * (8+x)(9+y*2).F000.3F40 PCIy INteruppt ACK1
113: *
114: * (8+x)(9+y*2).F000.3F80 N/A Unused
115: * - (8+x)(9+y*2).FFFF.FFFF
116: *
117: */
118:
119: /*
120: * MC-PCI Bus Bridge CSRs
121: *
122: * Address Map Overview:
123: *
124: * Offset Selected Space
125: * ---------------- -------------------------------------------------
126: * 0x00000000 General config, control, diag, error logging regs.
127: * 0x00001000 PCI Error Status
128: * 0x00001300 PCI Scatter/Gather Regs.
129: * 0x00001800 Scatter/Gather TLB Regs.
130: * 0x00004000 MDPA Error Status & Diagnostic Control
131: * 0x00008000 MDPB Error Status & Diagnostic Control
132: * 0x000E0000 - Flash Rom Space --
133: * 0x000FFFFF offset address into PCI Dense Mem Space
134: * 0x10003F00 Interrupt Acknowledge
135: *
136: */
137:
138:
139: /*
140: * Address Space Cookies
141: */
142:
143: #define MCPCIA_PCI_SPARSE 0x000000000UL
144: #define MCPCIA_PCI_DENSE 0x100000000UL
145: #define MCPCIA_PCI_IOSPACE 0x180000000UL
146: #define MCPCIA_PCI_CONF 0x1C0000000UL
147: #define MCPCIA_PCI_BRIDGE 0x1E0000000UL
148: #define MCPCIA_PCI_IACK 0x1F0000000UL
149:
150: /*
151: * MCPCIA Bus Bridge Registers
152: *
153: * These are offsets that don't include GBUS, MID, or address space offsets.
154: */
155:
156: #define _MCPCIA_PCI_REV 0x000000000 /* PCI Revision Register (R) */
157: #define _MCPCIA_WHOAMI 0x000000040 /* PCI Who Am I (R) */
158: #define _MCPCIA_PCI_LAT 0x000000080 /* PCI Latency Timer (RW) */
159: #define _MCPCIA_CAP_CTRL 0x000000100 /* PCI Bridge Control (RW) */
160: #define _MCPCIA_HAE_MEM 0x000000400 /* PCI HAE Sparse Memory (RW) */
161: #define _MCPCIA_HAE_IO 0x000000440 /* PCI HAE Sparse I/O (RW) */
162: #define _MCPCIA_IACK_SC 0x000000480 /* PCI Special Cycle Ack */
163: #define _MCPCIA_HAE_DENSE 0x0000004C0 /* PCI HAE Dense Memory (RW) */
164:
165: #define _MCPCIA_INT_CTL 0x000000500 /* PCI Interrupt Control */
166: #define _MCPCIA_INT_REQ 0x000000540 /* PCI Interrupt Request */
167: #define _MCPCIA_INT_TARG 0x000000580 /* PCI Int Tgt Devices */
168: #define _MCPCIA_INT_ADR 0x0000005C0 /* PCI Int Tgt Address */
169: #define _MCPCIA_INT_ADR_EXT 0x000000600 /* PCI Int Tgt Addr Ext */
170: #define _MCPCIA_INT_MASK0 0x000000640 /* PCI Int Mask 0 */
171: #define _MCPCIA_INT_MASK1 0x000000680 /* PCI Int Mask 1 */
172:
173: #define _MCPCIA_INT_ACK0 0x100003F00 /* PCI Int Ack 0 */
174: #define _MCPCIA_INT_ACK1 0x100003F40 /* PCI Int Ack 1 */
175:
176: #define _MCPCIA_PERF_MON 0x000000300 /* PCI Perf Monitor */
177: #define _MCPCIA_PERF_CONT 0x000000340 /* PCI Perf Monitor Control */
178:
179: #define _MCPCIA_CAP_DIAG 0x000000700 /* MC-PCI Diagnostic Control */
180: #define _MCPCIA_SCRATCH0 0x000000740 /* Diag General */
181: #define _MCPCIA_SCRATCH1 0x000000780 /* Diag General */
182: #define _MCPCIA_TOM 0x0000007C0 /* Top Of Memory */
183: #define _MCPCIA_MC_ERR0 0x000000800 /* MC Err Info 0 */
184: #define _MCPCIA_MC_ERR1 0x000000840 /* MC Err Info 1 */
185: #define _MCPCIA_CAP_ERR 0x000000880 /* CAP Error Register */
186:
187: #define _MCPCIA_PCI_ERR1 0x000001040 /* PCI Error Status */
188:
189: #define _MCPCIA_MDPA_STAT 0x000004000 /* MDPA Status */
190: #define _MCPCIA_MDPA_SYN 0x000004040 /* MDPA Syndrome */
191: #define _MCPCIA_MDPA_DIAG 0x000004080 /* Diag Check MDPA */
192:
193: #define _MCPCIA_MDPB_STAT 0x000008000 /* MDPB Status */
194: #define _MCPCIA_MDPB_SYN 0x000008040 /* MDPB Syndrome */
195: #define _MCPCIA_MDPB_DIAG 0x000008080 /* Diag Check MDPB */
196:
197: #define _MCPCIA_SG_TBIA 0x000001300 /* Scatter/Gather TBIA */
198: #define _MCPCIA_HBASE 0x000001340 /* PC "Hole" Compatibility */
199: #define _MCPCIA_W0_BASE 0x000001400 /* Window Base 0 */
200: #define _MCPCIA_W0_MASK 0x000001440 /* Window Mask 0 */
201: #define _MCPCIA_T0_BASE 0x000001480 /* Translated Base 0 */
202: #define _MCPCIA_W1_BASE 0x000001500 /* Window Base 1 */
203: #define _MCPCIA_W1_MASK 0x000001540 /* Window Mask 1 */
204: #define _MCPCIA_T1_BASE 0x000001580 /* Translated Base 1 */
205: #define _MCPCIA_W2_BASE 0x000001600 /* Window Base 2 */
206: #define _MCPCIA_W2_MASK 0x000001640 /* Window Mask 2 */
207: #define _MCPCIA_T2_BASE 0x000001680 /* Translated Base 2 */
208: #define _MCPCIA_W3_BASE 0x000001700 /* Window Base 3 */
209: #define _MCPCIA_W3_MASK 0x000001740 /* Window Mask 3 */
210: #define _MCPCIA_T3_BASE 0x000001780 /* Translated Base 3 */
211: #define _MCPCIA_W_DAC 0x0000017C0 /* Window DAC Base */
212:
213:
214: /*
215: * Handier defines- uses precalculated offset in softc.
216: */
217: #define _SYBRIDGE(ccp) ((ccp)->cc_sysbase | MCPCIA_PCI_BRIDGE)
218:
219: #define MCPCIA_PCI_REV(ccp) (_SYBRIDGE(ccp) | _MCPCIA_PCI_REV)
220: #define MCPCIA_WHOAMI(ccp) (_SYBRIDGE(ccp) | _MCPCIA_WHOAMI)
221: #define MCPCIA_PCI_LAT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_PCI_LAT)
222: #define MCPCIA_CAP_CTRL(ccp) (_SYBRIDGE(ccp) | _MCPCIA_CAP_CTRL)
223: #define MCPCIA_HAE_MEM(ccp) (_SYBRIDGE(ccp) | _MCPCIA_HAE_MEM)
224: #define MCPCIA_HAE_IO(ccp) (_SYBRIDGE(ccp) | _MCPCIA_HAE_IO)
225: #define MCPCIA_IACK_SC(ccp) (_SYBRIDGE(ccp) | _MCPCIA_IACK_SC)
226: #define MCPCIA_HAE_DENSE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_HAE_DENSE)
227: #define MCPCIA_INT_CTL(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_CTL)
228: #define MCPCIA_INT_REQ(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_REQ)
229: #define MCPCIA_INT_TARG(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_TARG)
230: #define MCPCIA_INT_ADR(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ADR)
231: #define MCPCIA_INT_ADR_EXT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ADR_EXT)
232: #define MCPCIA_INT_MASK0(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_MASK0)
233: #define MCPCIA_INT_MASK1(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_MASK1)
234: #define MCPCIA_INT_ACK0(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ACK0)
235: #define MCPCIA_INT_ACK1(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ACK1)
236: #define MCPCIA_PERF_MON(ccp) (_SYBRIDGE(ccp) | _MCPCIA_PERF_MON)
237: #define MCPCIA_PERF_CONT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_PERF_CONT)
238: #define MCPCIA_CAP_DIAG(ccp) (_SYBRIDGE(ccp) | _MCPCIA_CAP_DIAG)
239: #define MCPCIA_SCRATCH0(ccp) (_SYBRIDGE(ccp) | _MCPCIA_SCRATCH0)
240: #define MCPCIA_SCRATCH1(ccp) (_SYBRIDGE(ccp) | _MCPCIA_SCRATCH1)
241: #define MCPCIA_TOM(ccp) (_SYBRIDGE(ccp) | _MCPCIA_TOM)
242: #define MCPCIA_MC_ERR0(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MC_ERR0)
243: #define MCPCIA_MC_ERR1(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MC_ERR1)
244: #define MCPCIA_CAP_ERR(ccp) (_SYBRIDGE(ccp) | _MCPCIA_CAP_ERR)
245: #define MCPCIA_PCI_ERR1(ccp) (_SYBRIDGE(ccp) | _MCPCIA_PCI_ERR1)
246: #define MCPCIA_MDPA_STAT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MDPA_STAT)
247: #define MCPCIA_MDPA_SYN(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MDPA_SYN)
248: #define MCPCIA_MDPA_DIAG(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MDPA_DIAG)
249: #define MCPCIA_MDPB_STAT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MDPB_STAT)
250: #define MCPCIA_MDPB_SYN(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MDPB_SYN)
251: #define MCPCIA_MDPB_DIAG(ccp) (_SYBRIDGE(ccp) | _MCPCIA_MDPB_DIAG)
252: #define MCPCIA_SG_TBIA(ccp) (_SYBRIDGE(ccp) | _MCPCIA_SG_TBIA)
253: #define MCPCIA_HBASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_HBASE)
254: #define MCPCIA_W0_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W0_BASE)
255: #define MCPCIA_W0_MASK(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W0_MASK)
256: #define MCPCIA_T0_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_T0_BASE)
257: #define MCPCIA_W1_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W1_BASE)
258: #define MCPCIA_W1_MASK(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W1_MASK)
259: #define MCPCIA_T1_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_T1_BASE)
260: #define MCPCIA_W2_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W2_BASE)
261: #define MCPCIA_W2_MASK(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W2_MASK)
262: #define MCPCIA_T2_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_T2_BASE)
263: #define MCPCIA_W3_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W3_BASE)
264: #define MCPCIA_W3_MASK(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W3_MASK)
265: #define MCPCIA_T3_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_T3_BASE)
266: #define MCPCIA_W_DAC(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W_DAC)
267:
268: /*
269: * This is here for what error handling will get as a collected subpacket.
270: */
271:
272: struct mcpcia_iodsnap {
273: u_int64_t base_addr;
274: u_int32_t whami;
275: u_int32_t rsvd0;
276: u_int32_t pci_rev;
277: u_int32_t cap_ctrl;
278: u_int32_t hae_mem;
279: u_int32_t hae_io;
280: u_int32_t int_ctl;
281: u_int32_t int_reg;
282: u_int32_t int_mask0;
283: u_int32_t int_mask1;
284: u_int32_t mc_err0;
285: u_int32_t mc_err1;
286: u_int32_t cap_err;
287: u_int32_t sys_env;
288: u_int32_t pci_err1;
289: u_int32_t mdpa_stat;
290: u_int32_t mdpa_syn;
291: u_int32_t mdpb_stat;
292: u_int32_t mdpb_syn;
293: u_int32_t rsvd2;
294: u_int32_t rsvd3;
295: u_int32_t rsvd4;
296: };
297:
298: /*
299: * PCI_REV Register definitions
300: */
301: #define CAP_REV(reg) ((reg) & 0xf)
302: #define HORSE_REV(reg) (((reg) >> 4) & 0xf)
303: #define SADDLE_REV(reg) (((reg) >> 8) & 0xf)
304: #define SADDLE_TYPE(reg) (((reg) >> 12) & 0x3)
305: #define EISA_PRESENT(reg) ((reg) & (1 << 15))
306: #define IS_MCPCIA_MAGIC(reg) (((reg) & 0xffff0000) == 0x6000000)
307:
308:
309: /*
310: * WHOAMI Register definitions
311: *
312: * The Device ID is an echo of the MID of the CPU reading this register-
313: * cheezy way to figure out who you are (ask someone else!).
314: */
315: #define MCBUS_CPU_MID(x) ((x) & 0x7)
316: #define MCBUS_CPU_INFO(x) (((x) >> 6) & 0xff)
317: #define CPU_Fill_Err 0x80
318: #define CPU_DTAG_Perr 0x40
319: #define CPU_RevMask 0x38
320: #define CPU_RevShift 3
321: #define CPU_BCacheMask 0x3
322: #define CPU_BCache_0MB 0
323: #define CPU_BCache_1MB 1
324: #define CPU_BCache_2MB 2
325: #define CPU_BCache_4MB 3
326:
327: /*
328: * PCI Latency Register Definitions
329: */
330: #define PCI_LAT_SHIFT 8 /* it's in the 2nd byte. */
331:
332: /*
333: * CAP Control Register Definitions
334: */
335: #define CAP_LED_ON 0x00000001 /* Selftest LED passed */
336: #define CAP_EV56_BW_EN 0x00000002 /* BW Enables (EV56, EV6 only) */
337: #define CAP_DLY_RD_EN 0x00000010 /* PCI Delayed Reads Enabled */
338: #define CAP_MEM_EN 0x00000020 /* Respond to PCI transactions */
339: #define CAP_REQ64_EN 0x00000040 /* Request 64 bit data transactions */
340: #define CAP_ACK64_EN 0x00000080 /* Respond to 64 bit data "" */
341: #define CAP_ADR_PAR_EN 0x00000100 /* Check PCI address Parity */
342: #define CAP_MC_CA_PAR 0x00000200 /* Check MC bus CMD/Address Parity */
343: #define CAP_MC_NXM_EN 0x00000400 /* Check for MC NXM */
344: #define CAP_BUS_MON 0x00000800 /* Check for PCI errs (as bystander) */
345: /* bits 19:16 control number of pending write transactions */
346: #define SHORT 0
347: #define MED 1
348: #define LONG 2
349: #define CAP_MEMRD_PREFETCH_SHIFT 20
350: #define CAP_MEMRDLN_PREFETCH_SHIFT 22
351: #define CAP_MEMRDMULT_PREFETCH_SHIFT 24
352: #define CAP_PARTIAL_WRITE (1 << 26)
353:
354: #define CAP_ARB_BPRI 0x00000000 /* Bridge Priority Arb */
355: #define CAP_ARB_RROBIN 0x40000000 /* "" Round Robin */
356: #define CAP_ARB_RROBIN1 0x80000000 /* "" Round Robin #1 */
357:
358: /*
359: * Diagnostic Register Bits
360: */
361: /* CAP_DIAG register */
362: #define CAP_DIAG_PCIRESET 0x1 /*
363: * WriteOnly. Assert 1 for 100usec min.,
364: * then write zero. NOTE: deadlocks
365: * exist in h/w if anything but this
366: * register is accessed while reset
367: * is asserted.
368: */
369: #define CAP_DIAG_MC_ADRPE (1<<30) /* Invert MC Bus Address/Parity */
370: #define CAP_DIAG_PCI_ADRPE (1<<31) /* Force bad PCI parity (low 32) */
371:
372: /* MDPA_DIAG or MDPB_DIAG registers */
373: #define MDPX_ECC_ENA (1<<28) /* Enable ECC on MC Bus (default 1) */
374: #define MDPX_PAR_ENA (1<<29) /* Enable Parity on PCI (default 0) */
375: #define MDPX_DIAG_FPE_PCI (1<<30) /* Force PCI parity error */
376: #define MDPX_DIAG_USE_CHK (1<<31) /*
377: * When set, DMA write cycles use the
378: * value in the low 8 bits of this
379: * register (MDPA or MDPB) as ECC
380: * sent onto main memory.
381: */
382:
383: /*
384: * Interrupt Specific bits...
385: *
386: * Mostly we don't have to mess with any of the interrupt specific registers
387: * as the SRM has set most of this pretty complex stuff up for us.
388: *
389: * However, to enable specific interrupts, we need to set some bits
390: * in imask0 if we want to have them vectored to PALcode for appropriate
391: * dispatch.
392: */
393:
394: /*
395: * bits 0-15 correspond to 4 slots (time 4 buspins) for each PCI bus.
396: * bit 16 is the NCR810 onboard SCSI interrupt.
397: * bits 19-20 are reserved.
398: */
399:
400: #define MCPCIA_I2C_CTRL_INTR (1<<17)
401: #define MCPCIA_I2C_CTRL_BUS_ERR (1<<18)
402:
403: #define MCPCIA_8259_NMI_INTR (1<<21)
404: #define MCPCIA_SOFT_ERR_INTR (1<<22)
405: #define MCPCIA_HARD_ERR_INTR (1<<23)
406:
407: #ifdef YET
408: #define MCPCIA_GEN_IENABL \
409: (MCPCIA_I2C_CTRL_BUS_ERR|MCPCIA_SOFT_ERR_INTR|MCPCIA_HARD_ERR_INTR)
410: #else
411: #define MCPCIA_GEN_IENABL \
412: (MCPCIA_SOFT_ERR_INTR|MCPCIA_HARD_ERR_INTR)
413: #endif
414:
415: /*
416: * DMA Address Specific bits...
417: */
418:
419: #define MCPCIA_WBASE_EN 0x1
420: #define MCPCIA_WBASE_SG 0x2
421: #define MCPCIA_WBASE_DAC 0x8
422: #define MCPCIA_WBASE_BSHIFT 20
423:
424: #define MCPCIA_WMASK_1M 0x00000000
425: #define MCPCIA_WMASK_2M 0x00100000
426: #define MCPCIA_WMASK_4M 0x00300000
427: #define MCPCIA_WMASK_8M 0x00700000
428: #define MCPCIA_WMASK_16M 0x00f00000
429: #define MCPCIA_WMASK_32M 0x01f00000
430: #define MCPCIA_WMASK_64M 0x03f00000
431: #define MCPCIA_WMASK_128M 0x07f00000
432: #define MCPCIA_WMASK_256M 0x0ff00000
433: #define MCPCIA_WMASK_512M 0x1ff00000
434: #define MCPCIA_WMASK_1G 0x3ff00000
435: #define MCPCIA_WMASK_2G 0x7ff00000
436: #define MCPCIA_WMASK_4G 0xfff00000
437:
438: /*
439: * The WBASEX register contains bits 39:10 of a physical address
440: * shifted to bits 31:2 of this 32 bit register. Namely, shifted
441: * right by 8 bits.
442: */
443: #define MCPCIA_TBASEX_SHIFT 8
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to mcpciareg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / alpha / pci