Annotation of sys/arch/alpha/pci/lcareg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: lcareg.h,v 1.7 2001/02/16 16:02:54 jason Exp $ */
! 2: /* $NetBSD: lcareg.h,v 1.7 1997/06/06 23:54:31 thorpej Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1995 Carnegie-Mellon University.
! 6: * All rights reserved.
! 7: *
! 8: * Authors: Jeffrey Hsu, Jason R. Thorpe
! 9: *
! 10: * Permission to use, copy, modify and distribute this software and
! 11: * its documentation is hereby granted, provided that both the copyright
! 12: * notice and this permission notice appear in all copies of the
! 13: * software, derivative works or modified versions, and any portions
! 14: * thereof, and that both notices appear in supporting documentation.
! 15: *
! 16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
! 17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
! 18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 19: *
! 20: * Carnegie Mellon requests users of this software to return to
! 21: *
! 22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 23: * School of Computer Science
! 24: * Carnegie Mellon University
! 25: * Pittsburgh PA 15213-3890
! 26: *
! 27: * any improvements or extensions that they make and grant Carnegie the
! 28: * rights to redistribute these changes.
! 29: */
! 30:
! 31: /*
! 32: * 21066 chip registers
! 33: */
! 34:
! 35: #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
! 36: #define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r))
! 37:
! 38: /*
! 39: * Base addresses
! 40: */
! 41: #define LCA_IOC_BASE 0x180000000L /* LCA IOC Regs */
! 42: #define LCA_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */
! 43: #define LCA_PCI_CONF 0x1e0000000L /* PCI Conf. Space */
! 44: #define LCA_PCI_SPARSE 0x200000000L /* PCI Sparse Space */
! 45: #define LCA_PCI_DENSE 0x300000000L /* PCI Dense Space */
! 46:
! 47: #define LCA_IOC_HAE LCA_IOC_BASE /* Host Address Ext. (64) */
! 48: #define IOC_HAE_ADDREXT 0x00000000f8000000UL
! 49: #define IOC_HAE_RSVSD 0xffffffff07ffffffUL
! 50:
! 51: #define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */
! 52:
! 53: #define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */
! 54: #define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */
! 55: #define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */
! 56: #define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */
! 57: #define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */
! 58: #define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */
! 59: #define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */
! 60: #define IOC_STAT0_CODESHIFT 8
! 61: #define IOC_STAT0_P_NBR 0x00000000ffffe000UL /* page number mask */
! 62:
! 63: #define LCA_IOC_STAT1 (LCA_IOC_BASE + 0x060) /* Status 1 */
! 64: #define IOC_STAT1_ADDR 0x00000000ffffffffUL /* PCI address mask */
! 65:
! 66: #define LCA_IOC_TBIA (LCA_IOC_BASE + 0x080) /* TLB Invalidate All */
! 67: #define LCA_IOC_TB_ENA (LCA_IOC_BASE + 0x0a0) /* TLB Enable */
! 68: #define IOC_TB_ENA_TEN 0x0000000000000080UL
! 69:
! 70: #define LCA_IOC_W_BASE0 (LCA_IOC_BASE + 0x100) /* Window Base */
! 71: #define LCA_IOC_W_MASK0 (LCA_IOC_BASE + 0x140) /* Window Mask */
! 72: #define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */
! 73:
! 74: #define LCA_IOC_W_BASE1 (LCA_IOC_BASE + 0x120) /* Window Base */
! 75: #define LCA_IOC_W_MASK1 (LCA_IOC_BASE + 0x160) /* Window Mask */
! 76: #define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */
! 77:
! 78: #define IOC_W_BASE_W_BASE 0x00000000fff00000UL /* Window base value */
! 79: #define IOC_W_BASE_SG 0x0000000100000000UL /* Window uses SGMAPs */
! 80: #define IOC_W_BASE_WEN 0x0000000200000000UL /* Window enable */
! 81:
! 82: #define IOC_W_MASK_1M 0x0000000000000000UL /* 1MB window */
! 83: #define IOC_W_MASK_2M 0x0000000000100000UL /* 2MB window */
! 84: #define IOC_W_MASK_4M 0x0000000000300000UL /* 4MB window */
! 85: #define IOC_W_MASK_8M 0x0000000000700000UL /* 8MB window */
! 86: #define IOC_W_MASK_16M 0x0000000000f00000UL /* 16MB window */
! 87: #define IOC_W_MASK_32M 0x0000000001f00000UL /* 32MB window */
! 88: #define IOC_W_MASK_64M 0x0000000003f00000UL /* 64MB window */
! 89: #define IOC_W_MASK_128M 0x0000000007f00000UL /* 128M window */
! 90: #define IOC_W_MASK_256M 0x000000000ff00000UL /* 256M window */
! 91: #define IOC_W_MASK_512M 0x000000001ff00000UL /* 512M window */
! 92: #define IOC_W_MASK_1G 0x000000003ff00000UL /* 1GB window */
! 93: #define IOC_W_MASK_2G 0x000000007ff00000UL /* 2GB window */
! 94: #define IOC_W_MASK_4G 0x00000000fff00000UL /* 4GB window */
! 95:
! 96: #define IOC_W_T_BASE 0x00000000fffffc00UL /* page table base */
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