Annotation of sys/arch/alpha/pci/irongatereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: irongatereg.h,v 1.2 2001/04/17 14:53:33 art Exp $ */
2: /* $NetBSD: irongatereg.h,v 1.2 2000/06/26 02:42:10 thorpej Exp $ */
3:
4: /*-
5: * Copyright (c) 2000 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * Register definitions for the AMD 751 (``Irongate'') core logic
42: * chipset.
43: */
44:
45: /*
46: * Address map.
47: *
48: * This from the Tsunami address map:
49: * EV6 has a new superpage which can pass through 44 address bits. (Umm, a
50: * superduperpage?) But, the firmware doesn't turn it on, so we use the old
51: * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
52: * the needed I/O space access. This is just as well; it means we don't have
53: * to worry about which GENERIC code might get called on other CPU models.
54: *
55: * E.g., we want this: 0x0801##fc00##0000
56: * We use this: 0x0101##fc00##0000
57: * ...mix in the old SP: 0xffff##fc00##0000##0000
58: * ...after PA sign ext: 0xffff##ff01##fc00##0000
59: * (PA<42:41> ignored)
60: *
61: * PCI memory and RAM: 0000.0000.0000
62: * IACK 0001.f800.0000
63: * PCI I/O: 0001.fc00.0000
64: * AMD 751 (also in PCI config space): 0001.fe00.0000
65: */
66:
67: /*
68: * This hack allows us to map the I/O address space without using
69: * the KSEG sign extension hack.
70: */
71: #define IRONGATE_PHYSADDR(x) \
72: (((x) & ~0x0100##0000##0000) | 0x0800##0000##0000)
73:
74: #define IRONGATE_KSEG_BIAS 0x0100##0000##0000UL
75:
76: #define IRONGATE_MEM_BASE (IRONGATE_KSEG_BIAS | 0x0000##0000##0000UL)
77: #define IRONGATE_IACK_BASE (IRONGATE_KSEG_BIAS | 0x0001##f800##0000UL)
78: #define IRONGATE_IO_BASE (IRONGATE_KSEG_BIAS | 0x0001##fc00##0000UL)
79: #define IRONGATE_SELF_BASE (IRONGATE_KSEG_BIAS | 0x0001##fe00##0000UL)
80:
81: /*
82: * PCI configuration register access using done by using
83: * ``configuration mode 1'' (in PC lingo), using the I/O
84: * space addresses described in the PCI Local Bus Specification
85: * Revision 2.2.
86: */
87: #define IRONGATE_CONFADDR 0x0cf8
88: #define IRONGATE_CONFDATA 0x0cfc
89:
90: #define CONFADDR_ENABLE 0x80000000U
91:
92: /*
93: * The AMD 751 PCI-Host bridge is located at device 0, and the
94: * AGP controller (seen as a PCI-PCI bridge) is at device 1.
95: */
96: #define IRONGATE_PCIHOST_DEV 0
97: #define IRONGATE_PCIAGP_DEV 1
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