Annotation of sys/arch/alpha/pci/cia.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cia.c,v 1.23 2006/12/14 17:36:12 kettenis Exp $ */
2: /* $NetBSD: cia.c,v 1.56 2000/06/29 08:58:45 mrg Exp $ */
3:
4: /*-
5: * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: /*
42: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
43: * All rights reserved.
44: *
45: * Author: Chris G. Demetriou
46: *
47: * Permission to use, copy, modify and distribute this software and
48: * its documentation is hereby granted, provided that both the copyright
49: * notice and this permission notice appear in all copies of the
50: * software, derivative works or modified versions, and any portions
51: * thereof, and that both notices appear in supporting documentation.
52: *
53: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
54: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
55: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
56: *
57: * Carnegie Mellon requests users of this software to return to
58: *
59: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
60: * School of Computer Science
61: * Carnegie Mellon University
62: * Pittsburgh PA 15213-3890
63: *
64: * any improvements or extensions that they make and grant Carnegie the
65: * rights to redistribute these changes.
66: */
67:
68: #include <sys/param.h>
69: #include <sys/systm.h>
70: #include <sys/kernel.h>
71: #include <sys/malloc.h>
72: #include <sys/device.h>
73: #include <uvm/uvm_extern.h>
74:
75: #include <machine/autoconf.h>
76: #include <machine/rpb.h>
77:
78: #include <dev/isa/isareg.h>
79: #include <dev/isa/isavar.h>
80:
81: #include <dev/pci/pcireg.h>
82: #include <dev/pci/pcivar.h>
83: #include <alpha/pci/ciareg.h>
84: #include <alpha/pci/ciavar.h>
85:
86: #ifdef DEC_KN20AA
87: #include <alpha/pci/pci_kn20aa.h>
88: #endif
89: #ifdef DEC_EB164
90: #include <alpha/pci/pci_eb164.h>
91: #endif
92: #ifdef DEC_550
93: #include <alpha/pci/pci_550.h>
94: #endif
95: #ifdef DEC_1000A
96: #include <alpha/pci/pci_1000a.h>
97: #endif
98: #ifdef DEC_1000
99: #include <alpha/pci/pci_1000.h>
100: #endif
101:
102: int ciamatch(struct device *, void *, void *);
103: void ciaattach(struct device *, struct device *, void *);
104:
105: struct cfattach cia_ca = {
106: sizeof(struct device), ciamatch, ciaattach,
107: };
108:
109: struct cfdriver cia_cd = {
110: NULL, "cia", DV_DULL,
111: };
112:
113: static int ciaprint(void *, const char *pnp);
114:
115: /* There can be only one. */
116: int ciafound;
117: struct cia_config cia_configuration;
118:
119: /*
120: * This determines if we attempt to use BWX for PCI bus and config space
121: * access. Some systems, notably with Pyxis, don't fare so well unless
122: * BWX is used.
123: *
124: * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!).
125: * So, we decouple the uses for PCI config space and PCI bus space.
126: *
127: * FURTHERMORE! The Pyxis, most notably earlier revs, really don't
128: * do so well if you don't use BWX for bus access. So we default to
129: * forcing BWX on those chips.
130: *
131: * Geez.
132: */
133:
134: #ifndef CIA_PCI_USE_BWX
135: #define CIA_PCI_USE_BWX 1
136: #endif
137:
138: #ifndef CIA_BUS_USE_BWX
139: #define CIA_BUS_USE_BWX 1
140: #endif
141:
142: #ifndef CIA_PYXIS_FORCE_BWX
143: #define CIA_PYXIS_FORCE_BWX 1
144: #endif
145:
146: int cia_pci_use_bwx = CIA_PCI_USE_BWX;
147: int cia_bus_use_bwx = CIA_BUS_USE_BWX;
148: int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX;
149:
150: int
151: ciamatch(parent, match, aux)
152: struct device *parent;
153: void *match;
154: void *aux;
155: {
156: struct mainbus_attach_args *ma = aux;
157:
158: /* Make sure that we're looking for a CIA. */
159: if (strcmp(ma->ma_name, cia_cd.cd_name) != 0)
160: return (0);
161:
162: if (ciafound)
163: return (0);
164:
165: return (1);
166: }
167:
168: /*
169: * Set up the chipset's function pointers.
170: */
171: void
172: cia_init(ccp, mallocsafe)
173: struct cia_config *ccp;
174: int mallocsafe;
175: {
176: int pci_use_bwx = cia_pci_use_bwx;
177: int bus_use_bwx = cia_bus_use_bwx;
178:
179: ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
180: ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
181: ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
182:
183: /*
184: * Determine if we have a Pyxis. Only two systypes can
185: * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
186: * and the DEC_550 systype (Miata).
187: */
188: if ((cputype == ST_EB164 &&
189: (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
190: cputype == ST_DEC_550) {
191: ccp->cc_flags |= CCF_ISPYXIS;
192: if (cia_pyxis_force_bwx)
193: pci_use_bwx = bus_use_bwx = 1;
194: }
195:
196: /*
197: * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
198: */
199: if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0)
200: ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG);
201: else
202: ccp->cc_cnfg = 0;
203:
204: /*
205: * Use BWX iff:
206: *
207: * - It hasn't been disabled by the user,
208: * - it's enabled in CNFG,
209: * - we're implementation version ev5,
210: * - BWX is enabled in the CPU's capabilities mask (yes,
211: * the bit is really cleared if the capability exists...)
212: */
213: if ((pci_use_bwx || bus_use_bwx) &&
214: (ccp->cc_cnfg & CNFG_BWEN) != 0 &&
215: (cpu_amask & ALPHA_AMASK_BWX) != 0) {
216: u_int32_t ctrl;
217:
218: if (pci_use_bwx)
219: ccp->cc_flags |= CCF_PCI_USE_BWX;
220: if (bus_use_bwx)
221: ccp->cc_flags |= CCF_BUS_USE_BWX;
222:
223: /*
224: * For whatever reason, the firmware seems to enable PCI
225: * loopback mode if it also enables BWX. Make sure it's
226: * enabled if we have an old, buggy firmware rev.
227: */
228: alpha_mb();
229: ctrl = REGVAL(CIA_CSR_CTRL);
230: if ((ctrl & CTRL_PCI_LOOP_EN) == 0) {
231: REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
232: alpha_mb();
233: }
234: }
235:
236: if (!ccp->cc_initted) {
237: /* don't do these twice since they set up extents */
238: if (ccp->cc_flags & CCF_BUS_USE_BWX) {
239: cia_bwx_bus_io_init(&ccp->cc_iot, ccp);
240: cia_bwx_bus_mem_init(&ccp->cc_memt, ccp);
241: } else {
242: cia_bus_io_init(&ccp->cc_iot, ccp);
243: cia_bus_mem_init(&ccp->cc_memt, ccp);
244: }
245: }
246: ccp->cc_mallocsafe = mallocsafe;
247:
248: cia_pci_init(&ccp->cc_pc, ccp);
249: alpha_pci_chipset = &ccp->cc_pc;
250: alpha_pci_chipset->pc_name = "cia";
251: alpha_pci_chipset->pc_dense = CIA_PCI_DENSE;
252: alpha_pci_chipset->pc_hae_mask = 7L << 29;
253: if (ccp->cc_flags & CCF_BUS_USE_BWX) {
254: alpha_pci_chipset->pc_mem = CIA_EV56_BWMEM;
255: alpha_pci_chipset->pc_ports = CIA_EV56_BWIO;
256: alpha_pci_chipset->pc_bwx = 1;
257: } else {
258: alpha_pci_chipset->pc_mem = CIA_PCI_SMEM1;
259: alpha_pci_chipset->pc_ports = CIA_PCI_SIO1;
260: alpha_pci_chipset->pc_bwx = 0;
261: }
262:
263: ccp->cc_initted = 1;
264: }
265:
266: void
267: ciaattach(parent, self, aux)
268: struct device *parent, *self;
269: void *aux;
270: {
271: struct cia_config *ccp;
272: struct pcibus_attach_args pba;
273: const char *name;
274: int pass;
275:
276: /* note that we've attached the chipset; can't have 2 CIAs. */
277: ciafound = 1;
278:
279: /*
280: * set up the chipset's info; done once at console init time
281: * (maybe), but we must do it here as well to take care of things
282: * that need to use memory allocation.
283: */
284: ccp = &cia_configuration;
285: cia_init(ccp, 1);
286:
287: if (ccp->cc_flags & CCF_ISPYXIS) {
288: name = "Pyxis";
289: pass = ccp->cc_rev;
290: } else {
291: name = "ALCOR/ALCOR2";
292: pass = ccp->cc_rev + 1;
293: }
294:
295: printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n",
296: name, pass);
297:
298: if (ccp->cc_cnfg)
299: printf("%s: extended capabilities: %b\n", self->dv_xname,
300: ccp->cc_cnfg, CIA_CSR_CNFG_BITS);
301:
302: switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) {
303: case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX:
304: name = "PCI config and bus";
305: break;
306: case CCF_PCI_USE_BWX:
307: name = "PCI config";
308: break;
309: case CCF_BUS_USE_BWX:
310: name = "bus";
311: break;
312: default:
313: name = NULL;
314: break;
315: }
316: if (name != NULL)
317: printf("%s: using BWX for %s access\n", self->dv_xname, name);
318:
319: #ifdef DEC_550
320: if (cputype == ST_DEC_550 &&
321: (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
322: /*
323: * Miata 1 systems have a bug: DMA cannot cross
324: * an 8k boundary! Make sure PCI read prefetching
325: * is disabled on these chips. Note that secondary
326: * PCI busses don't have this problem, because of
327: * the way PPBs handle PCI read requests.
328: *
329: * In the 21174 Technical Reference Manual, this is
330: * actually documented as "Pyxis Pass 1", but apparently
331: * there are chips that report themselves as "Pass 1"
332: * which do not have the bug! Miatas with the Cypress
333: * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
334: * have the bug, so we use this check.
335: *
336: * NOTE: This bug is actually worked around in cia_dma.c,
337: * when direct-mapped DMA maps are created.
338: *
339: * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR
340: * XXX SGMAP DMA MAPPINGS!
341: */
342: u_int32_t ctrl;
343:
344: /* XXX no bets... */
345: printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n",
346: self->dv_xname);
347:
348: ccp->cc_flags |= CCF_PYXISBUG;
349:
350: alpha_mb();
351: ctrl = REGVAL(CIA_CSR_CTRL);
352: ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
353: REGVAL(CIA_CSR_CTRL) = ctrl;
354: alpha_mb();
355: }
356: #endif /* DEC_550 */
357:
358: cia_dma_init(ccp);
359:
360: switch (cputype) {
361: #ifdef DEC_KN20AA
362: case ST_DEC_KN20AA:
363: pci_kn20aa_pickintr(ccp);
364: break;
365: #endif
366:
367: #ifdef DEC_EB164
368: case ST_EB164:
369: pci_eb164_pickintr(ccp);
370: break;
371: #endif
372:
373: #ifdef DEC_550
374: case ST_DEC_550:
375: pci_550_pickintr(ccp);
376: break;
377: #endif
378:
379: #ifdef DEC_1000A
380: case ST_DEC_1000A:
381: pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
382: &ccp->cc_pc);
383: break;
384: #endif
385:
386: #ifdef DEC_1000
387: case ST_DEC_1000:
388: pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
389: &ccp->cc_pc);
390: break;
391: #endif
392:
393: default:
394: panic("ciaattach: shouldn't be here, really...");
395: }
396:
397: pba.pba_busname = "pci";
398: pba.pba_iot = &ccp->cc_iot;
399: pba.pba_memt = &ccp->cc_memt;
400: pba.pba_dmat =
401: alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI);
402: pba.pba_pc = &ccp->cc_pc;
403: pba.pba_domain = pci_ndomains++;
404: pba.pba_bus = 0;
405: pba.pba_bridgetag = NULL;
406:
407: #ifdef notyet
408: pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
409: if ((ccp->cc_flags & CCF_PYXISBUG) == 0)
410: pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
411: PCI_FLAGS_MWI_OKAY;
412: #endif
413: config_found(self, &pba, ciaprint);
414: }
415:
416: static int
417: ciaprint(aux, pnp)
418: void *aux;
419: const char *pnp;
420: {
421: register struct pcibus_attach_args *pba = aux;
422:
423: /* only PCIs can attach to CIAs; easy. */
424: if (pnp)
425: printf("%s at %s", pba->pba_busname, pnp);
426: printf(" bus %d", pba->pba_bus);
427: return (UNCONF);
428: }
429:
430: void
431: cia_pyxis_intr_enable(irq, onoff)
432: int irq, onoff;
433: {
434: u_int64_t imask;
435: int s;
436:
437: #if 0
438: printf("cia_pyxis_intr_enable: %s %d\n",
439: onoff ? "enabling" : "disabling", irq);
440: #endif
441:
442: s = splhigh();
443: alpha_mb();
444: imask = REGVAL64(PYXIS_INT_MASK);
445: if (onoff)
446: imask |= (1UL << irq);
447: else
448: imask &= ~(1UL << irq);
449: REGVAL64(PYXIS_INT_MASK) = imask;
450: alpha_mb();
451: splx(s);
452: }
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