Annotation of sys/arch/alpha/pci/apecsreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: apecsreg.h,v 1.6 2001/02/16 08:23:39 jason Exp $ */
! 2: /* $NetBSD: apecsreg.h,v 1.5.2.2 1997/06/06 20:26:53 thorpej Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1995 Carnegie-Mellon University.
! 6: * All rights reserved.
! 7: *
! 8: * Author: Chris G. Demetriou
! 9: *
! 10: * Permission to use, copy, modify and distribute this software and
! 11: * its documentation is hereby granted, provided that both the copyright
! 12: * notice and this permission notice appear in all copies of the
! 13: * software, derivative works or modified versions, and any portions
! 14: * thereof, and that both notices appear in supporting documentation.
! 15: *
! 16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
! 17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
! 18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 19: *
! 20: * Carnegie Mellon requests users of this software to return to
! 21: *
! 22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 23: * School of Computer Science
! 24: * Carnegie Mellon University
! 25: * Pittsburgh PA 15213-3890
! 26: *
! 27: * any improvements or extensions that they make and grant Carnegie the
! 28: * rights to redistribute these changes.
! 29: */
! 30:
! 31: /*
! 32: * APECS Chipset registers and constants.
! 33: *
! 34: * Taken from ``DECchip 21071 and DECchip 21072 Core Logic Chipsets Data
! 35: * Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38.
! 36: */
! 37:
! 38: #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
! 39:
! 40: /*
! 41: * Base addresses
! 42: */
! 43: #define COMANCHE_BASE 0x180000000L /* 21071-CA Regs */
! 44: #define EPIC_BASE 0x1a0000000L /* 21071-DA Regs */
! 45: #define APECS_PCI_IACK 0x1b0000000L /* PCI Int. Ack. */
! 46: #define APECS_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */
! 47: #define APECS_PCI_CONF 0x1e0000000L /* PCI Conf. Space */
! 48: #define APECS_PCI_SPARSE 0x200000000L /* PCI Sparse Space */
! 49: #define APECS_PCI_DENSE 0x300000000L /* PCI Dense Space */
! 50:
! 51:
! 52: /*
! 53: * 21071-CA Registers
! 54: */
! 55:
! 56: /*
! 57: * 21071-CA General Registers
! 58: */
! 59: #define COMANCHE_GCR (COMANCHE_BASE + 0x0000) /* General Control */
! 60: #define COMANCHE_GCR_RSVD 0xc009
! 61: #define COMANCHE_GCR_SYSARB 0x0006
! 62: #define COMANCHE_GCR_WIDEMEM 0x0010
! 63: #define COMANCHE_GCR_BC_EN 0x0020
! 64: #define COMANCHE_GCR_BC_NOALLOC 0x0040
! 65: #define COMANCHE_GCR_BC_LONGWR 0x0080
! 66: #define COMANCHE_GCR_BC_IGNTAG 0x0100
! 67: #define COMANCHE_GCR_BC_FRCTAG 0x0200
! 68: #define COMANCHE_GCR_BC_FRCD 0x0400
! 69: #define COMANCHE_GCR_BC_FRCV 0x0800
! 70: #define COMANCHE_GCR_BC_FRCP 0x1000
! 71: #define COMANCHE_GCR_BC_BADAP 0x2000
! 72:
! 73: #define COMANCHE_RSVD (COMANCHE_BASE + 0x0020) /* Reserved */
! 74:
! 75: #define COMANCHE_ED (COMANCHE_BASE + 0x0040) /* Err & Diag Status */
! 76: #define COMANCHE_ED_LOSTERR 0x0001
! 77: #define COMANCHE_ED_BC_TAPERR 0x0002
! 78: #define COMANCHE_ED_BC_TCPERR 0x0004
! 79: #define COMANCHE_ED_NXMERR 0x0008
! 80: #define COMANCHE_ED_DMACAUSE 0x0010
! 81: #define COMANCHE_ED_VICCAUSE 0x0020
! 82: #define COMANCHE_ED_CREQCAUSE 0x01c0
! 83: #define COMANCHE_ED_RSVD 0x1e00
! 84: #define COMANCHE_ED_PASS2 0x2000
! 85: #define COMANCHE_ED_IDXLLOCK 0x4000
! 86: #define COMANCHE_ED_WRPEND 0x8000
! 87:
! 88: #define COMANCHE_TAGENB (COMANCHE_BASE + 0x0060) /* Tag Enable */
! 89: #define COMANCHE_TAGENB_RSVD 0x0001
! 90:
! 91: #define COMANCHE_TAGENB_C_4G 0x0000
! 92: #define COMANCHE_TAGENB_C_2G 0x8000
! 93: #define COMANCHE_TAGENB_C_1G 0xc000
! 94: #define COMANCHE_TAGENB_C_512M 0xe000
! 95: #define COMANCHE_TAGENB_C_256M 0xf000
! 96: #define COMANCHE_TAGENB_C_128M 0xf800
! 97: #define COMANCHE_TAGENB_C_64M 0xfc00
! 98: #define COMANCHE_TAGENB_C_32M 0xfe00
! 99: #define COMANCHE_TAGENB_C_16M 0xff00
! 100: #define COMANCHE_TAGENB_C_8M 0xff80
! 101: #define COMANCHE_TAGENB_C_4M 0xffc0
! 102: #define COMANCHE_TAGENB_C_2M 0xffe0
! 103: #define COMANCHE_TAGENB_C_1M 0xfff0
! 104: #define COMANCHE_TAGENB_C_512K 0xfff8
! 105: #define COMANCHE_TAGENB_C_256K 0xfffc
! 106: #define COMANCHE_TAGENB_C_128K 0xfffe
! 107:
! 108: #define COMANCHE_TAGENB_M_4G 0xffff
! 109: #define COMANCHE_TAGENB_M_2G 0x7fff
! 110: #define COMANCHE_TAGENB_M_1G 0x3fff
! 111: #define COMANCHE_TAGENB_M_512M 0x1fff
! 112: #define COMANCHE_TAGENB_M_256M 0x0fff
! 113: #define COMANCHE_TAGENB_M_128M 0x07ff
! 114: #define COMANCHE_TAGENB_M_64M 0x03ff
! 115: #define COMANCHE_TAGENB_M_32M 0x01ff
! 116: #define COMANCHE_TAGENB_M_16M 0x00ff
! 117: #define COMANCHE_TAGENB_M_8M 0x007f
! 118: #define COMANCHE_TAGENB_M_4M 0x003f
! 119: #define COMANCHE_TAGENB_M_2M 0x001f
! 120: #define COMANCHE_TAGENB_M_1M 0x000e
! 121: #define COMANCHE_TAGENB_M_512K 0x0006
! 122: #define COMANCHE_TAGENB_M_256K 0x0002
! 123: #define COMANCHE_TAGENB_M_128K 0x0000
! 124:
! 125: #define COMANCHE_ERR_LO (COMANCHE_BASE + 0x0080) /* Error Low Address */
! 126:
! 127: #define COMANCHE_ERR_HI (COMANCHE_BASE + 0x00a0) /* Error High Address */
! 128: #define COMANCHE_ERR_HI_RSVD 0xe000
! 129:
! 130: #define COMANCHE_LCK_LO (COMANCHE_BASE + 0x00c0) /* LDx_L Low Address */
! 131:
! 132: #define COMANCHE_LCK_HI (COMANCHE_BASE + 0x00e0) /* LDx_L High Address */
! 133: #define COMANCHE_LOCK_HI_RSVD 0xe000
! 134:
! 135: /*
! 136: * 21071-CA Memory Registers
! 137: */
! 138: #define COMANCHE_GTIM (COMANCHE_BASE + 0x0200) /* Global Timing */
! 139: #define COMANCHE_LOCK_HI_RSVD 0xe000
! 140:
! 141: #define COMANCHE_RTIM (COMANCHE_BASE + 0x0220) /* Refresh Timing */
! 142:
! 143: #define COMANCHE_VFP (COMANCHE_BASE + 0x0240) /* Video Frame Ptr. */
! 144: #define COMANCHE_VFP_COL 0x001f
! 145: #define COMANCHE_VFP_ROW 0x3fe0
! 146: #define COMANCHE_VFP_SUBBANK 0x4000
! 147: #define COMANCHE_VFP_RSVD 0x8000
! 148:
! 149: #define COMANCHE_PD_LO (COMANCHE_BASE + 0x0260) /* Pres Detect Low */
! 150:
! 151: #define COMANCHE_PD_HI (COMANCHE_BASE + 0x0280) /* Pres Detect High */
! 152:
! 153: /*
! 154: * 21071-CA Memory banks' Base Address Register format
! 155: */
! 156: #define COMANCHE_B0_BAR (COMANCHE_BASE + 0x0800) /* Bank 0 BA */
! 157: #define COMANCHE_B1_BAR (COMANCHE_BASE + 0x0820) /* Bank 1 BA */
! 158: #define COMANCHE_B2_BAR (COMANCHE_BASE + 0x0840) /* Bank 2 BA */
! 159: #define COMANCHE_B3_BAR (COMANCHE_BASE + 0x0860) /* Bank 3 BA */
! 160: #define COMANCHE_B4_BAR (COMANCHE_BASE + 0x0880) /* Bank 4 BA */
! 161: #define COMANCHE_B5_BAR (COMANCHE_BASE + 0x08a0) /* Bank 5 BA */
! 162: #define COMANCHE_B6_BAR (COMANCHE_BASE + 0x08c0) /* Bank 6 BA */
! 163: #define COMANCHE_B7_BAR (COMANCHE_BASE + 0x08e0) /* Bank 7 BA */
! 164: #define COMANCHE_B8_BAR (COMANCHE_BASE + 0x0900) /* Bank 8 BA */
! 165: #define COMANCHE_BAR_RSVD 0x001f
! 166:
! 167: /*
! 168: * 21071-CA Memory banks' Configuration Register format
! 169: */
! 170: #define COMANCHE_B0_CR (COMANCHE_BASE + 0x0a00) /* Bank 0 Config */
! 171: #define COMANCHE_B1_CR (COMANCHE_BASE + 0x0a20) /* Bank 1 Config */
! 172: #define COMANCHE_B2_CR (COMANCHE_BASE + 0x0a40) /* Bank 2 Config */
! 173: #define COMANCHE_B3_CR (COMANCHE_BASE + 0x0a60) /* Bank 3 Config */
! 174: #define COMANCHE_B4_CR (COMANCHE_BASE + 0x0a80) /* Bank 4 Config */
! 175: #define COMANCHE_B5_CR (COMANCHE_BASE + 0x0aa0) /* Bank 5 Config */
! 176: #define COMANCHE_B6_CR (COMANCHE_BASE + 0x0ac0) /* Bank 6 Config */
! 177: #define COMANCHE_B7_CR (COMANCHE_BASE + 0x0ae0) /* Bank 7 Config */
! 178: #define COMANCHE_B8_CR (COMANCHE_BASE + 0x0b00) /* Bank 8 Config */
! 179: #define COMANCHE_CR_VALID 0x0001
! 180: #define COMANCHE_CR_SIZE 0x001e
! 181: #define COMANCHE_CR_SUBENA 0x0020
! 182: #define COMANCHE_CR_COLSEL 0x01c0
! 183: #define COMANCHE_CR_S0_RSVD 0xfe00
! 184: #define COMANCHE_CR_S8_CHECK 0x0200
! 185: #define COMANCHE_CR_S8_RSVD 0xfc00
! 186:
! 187: /*
! 188: * 21071-CA Memory banks' Timing Register A format
! 189: */
! 190: #define COMANCHE_B0_TRA (COMANCHE_BASE + 0x0c00) /* Bank 0 Timing A */
! 191: #define COMANCHE_B1_TRA (COMANCHE_BASE + 0x0c20) /* Bank 1 Timing A */
! 192: #define COMANCHE_B2_TRA (COMANCHE_BASE + 0x0c40) /* Bank 2 Timing A */
! 193: #define COMANCHE_B3_TRA (COMANCHE_BASE + 0x0c60) /* Bank 3 Timing A */
! 194: #define COMANCHE_B4_TRA (COMANCHE_BASE + 0x0c80) /* Bank 4 Timing A */
! 195: #define COMANCHE_B5_TRA (COMANCHE_BASE + 0x0ca0) /* Bank 5 Timing A */
! 196: #define COMANCHE_B6_TRA (COMANCHE_BASE + 0x0cc0) /* Bank 6 Timing A */
! 197: #define COMANCHE_B7_TRA (COMANCHE_BASE + 0x0ce0) /* Bank 7 Timing A */
! 198: #define COMANCHE_B8_TRA (COMANCHE_BASE + 0x0d00) /* Bank 8 Timing A */
! 199: #define COMANCHE_TRA_ROWSETUP 0x0003
! 200: #define COMANCHE_TRA_ROWHOLD 0x000c
! 201: #define COMANCHE_TRA_COLSETUP 0x0070
! 202: #define COMANCHE_TRA_COLHOLD 0x0180
! 203: #define COMANCHE_TRA_RDLYROW 0x0e00
! 204: #define COMANCHE_TRA_RDLYCOL 0x7000
! 205: #define COMANCHE_TRA_RSVD 0x8000
! 206:
! 207: /*
! 208: * 21071-CA Memory banks' Timing Register B format
! 209: */
! 210: #define COMANCHE_B0_TRB (COMANCHE_BASE + 0x0e00) /* Bank 0 Timing B */
! 211: #define COMANCHE_B1_TRB (COMANCHE_BASE + 0x0e20) /* Bank 1 Timing B */
! 212: #define COMANCHE_B2_TRB (COMANCHE_BASE + 0x0e40) /* Bank 2 Timing B */
! 213: #define COMANCHE_B3_TRB (COMANCHE_BASE + 0x0e60) /* Bank 3 Timing B */
! 214: #define COMANCHE_B4_TRB (COMANCHE_BASE + 0x0e80) /* Bank 4 Timing B */
! 215: #define COMANCHE_B5_TRB (COMANCHE_BASE + 0x0ea0) /* Bank 5 Timing B */
! 216: #define COMANCHE_B6_TRB (COMANCHE_BASE + 0x0ec0) /* Bank 6 Timing B */
! 217: #define COMANCHE_B7_TRB (COMANCHE_BASE + 0x0ee0) /* Bank 7 Timing B */
! 218: #define COMANCHE_B8_TRB (COMANCHE_BASE + 0x0f00) /* Bank 8 Timing B */
! 219: #define COMANCHE_TRB_RTCAS 0x0007
! 220: #define COMANCHE_TRB_WTCAS 0x0038
! 221: #define COMANCHE_TRB_TCP 0x00c0
! 222: #define COMANCHE_TRB_WHOLD0ROW 0x0700
! 223: #define COMANCHE_TRB_WHOLD0COL 0x3800
! 224: #define COMANCHE_TRB_RSVD 0xc000
! 225:
! 226:
! 227: /*
! 228: * 21071-DA Registers
! 229: */
! 230: #define EPIC_DCSR (EPIC_BASE + 0x0000) /* Diagnostic CSR */
! 231: #define EPIC_DCSR_TENB 0x00000001
! 232: #define EPIC_DCSR_RSVD 0x7fc00082
! 233: #define EPIC_DCSR_PENB 0x00000004
! 234: #define EPIC_DCSR_DCEI 0x00000008
! 235: #define EPIC_DCSR_DPEC 0x00000010
! 236: #define EPIC_DCSR_IORT 0x00000020
! 237: #define EPIC_DCSR_LOST 0x00000040
! 238: #define EPIC_DCSR_DDPE 0x00000100
! 239: #define EPIC_DCSR_IOPE 0x00000200
! 240: #define EPIC_DCSR_TABT 0x00000400
! 241: #define EPIC_DCSR_NDEV 0x00000800
! 242: #define EPIC_DCSR_CMRD 0x00001000
! 243: #define EPIC_DCSR_UMRD 0x00002000
! 244: #define EPIC_DCSR_IPTL 0x00004000
! 245: #define EPIC_DCSR_MERR 0x00008000
! 246: #define EPIC_DCSR_DBYP 0x00030000
! 247: #define EPIC_DCSR_PCMD 0x003c0000
! 248: #define EPIC_DCSR_PASS2 0x80000000
! 249:
! 250: #define EPIC_PEAR (EPIC_BASE + 0x0020) /* PCI Err Addr. */
! 251:
! 252: #define EPIC_SEAR (EPIC_BASE + 0x0040) /* sysBus Err Addr. */
! 253: #define EPIC_SEAR_RSVD 0x0000000f
! 254: #define EPIC_SEAR_SYS_ERR 0xfffffff0
! 255:
! 256: #define EPIC_DUMMY_1 (EPIC_BASE + 0x0060) /* Dummy 1 */
! 257: #define EPIC_DUMMY_2 (EPIC_BASE + 0x0080) /* Dummy 2 */
! 258: #define EPIC_DUMMY_3 (EPIC_BASE + 0x00a0) /* Dummy 3 */
! 259:
! 260: #define EPIC_TBASE_1 (EPIC_BASE + 0x00c0) /* Trans. Base 1 */
! 261: #define EPIC_TBASE_2 (EPIC_BASE + 0x00e0) /* Trans. Base 2 */
! 262: #define EPIC_TBASE_RSVD 0x000001ff
! 263: #define EPIC_TBASE_T_BASE 0xfffffe00
! 264: #define EPIC_TBASE_SHIFT 1
! 265:
! 266: #define EPIC_PCI_BASE_1 (EPIC_BASE + 0x0100) /* PCI Base 1 */
! 267: #define EPIC_PCI_BASE_2 (EPIC_BASE + 0x0120) /* PCI Base 2 */
! 268: #define EPIC_PCI_BASE_RSVD 0x0003ffff
! 269: #define EPIC_PCI_BASE_SGEN 0x00040000
! 270: #define EPIC_PCI_BASE_WENB 0x00080000
! 271: #define EPIC_PCI_BASE_PCI_BASE 0xfff00000
! 272:
! 273: #define EPIC_PCI_MASK_1 (EPIC_BASE + 0x0140) /* PCI Mask 1 */
! 274: #define EPIC_PCI_MASK_2 (EPIC_BASE + 0x0160) /* PCI Mask 2 */
! 275: #define EPIC_PCI_MASK_RSVD 0x000fffff
! 276: #define EPIC_PCI_MASK_PCI_MASK 0xfff00000
! 277: #define EPIC_PCI_MASK_1M 0x00000000
! 278: #define EPIC_PCI_MASK_2M 0x00100000
! 279: #define EPIC_PCI_MASK_4M 0x00300000
! 280: #define EPIC_PCI_MASK_8M 0x00700000
! 281: #define EPIC_PCI_MASK_16M 0x00f00000
! 282: #define EPIC_PCI_MASK_32M 0x01f00000
! 283: #define EPIC_PCI_MASK_64M 0x03f00000
! 284: #define EPIC_PCI_MASK_128M 0x07f00000
! 285: #define EPIC_PCI_MASK_256M 0x0ff00000
! 286: #define EPIC_PCI_MASK_512M 0x1ff00000
! 287: #define EPIC_PCI_MASK_1G 0x3ff00000
! 288: #define EPIC_PCI_MASK_2G 0x7ff00000
! 289: #define EPIC_PCI_MASK_4G 0xfff00000
! 290:
! 291: #define EPIC_HAXR0 (EPIC_BASE + 0x0180) /* Host Addr Extn 0 */
! 292:
! 293: #define EPIC_HAXR1 (EPIC_BASE + 0x01a0) /* Host Addr Extn 1 */
! 294: #define EPIC_HAXR1_RSVD 0x07ffffff
! 295: #define EPIC_HAXR1_EADDR 0xf8000000
! 296:
! 297: #define EPIC_HAXR2 (EPIC_BASE + 0x01c0) /* Host Addr Extn 2 */
! 298: #define EPIC_HAXR2_CONF_TYPE 0x00000003
! 299: #define EPIC_HAXR2_CONF_TYPO0 0x00000000
! 300: #define EPIC_HAXR2_CONF_TYPE1 0x00000001
! 301: #define EPIC_HAXR2_RSVD 0x00fffffc
! 302: #define EPIC_HAXR2_EADDR 0xff000000
! 303:
! 304: #define EPIC_PMLT (EPIC_BASE + 0x01e0) /* PCI Mstr Lat Tmr */
! 305: #define EPIC_PMLT_PMLC 0x000000ff
! 306: #define EPIC_PMLT_RSVD 0xffffff00
! 307:
! 308: #define EPIC_TLB_TAG_0 (EPIC_BASE + 0x0200) /* TLB Tag 0 */
! 309: #define EPIC_TLB_TAG_1 (EPIC_BASE + 0x0220) /* TLB Tag 1 */
! 310: #define EPIC_TLB_TAG_2 (EPIC_BASE + 0x0240) /* TLB Tag 2 */
! 311: #define EPIC_TLB_TAG_3 (EPIC_BASE + 0x0260) /* TLB Tag 3 */
! 312: #define EPIC_TLB_TAG_4 (EPIC_BASE + 0x0280) /* TLB Tag 4 */
! 313: #define EPIC_TLB_TAG_5 (EPIC_BASE + 0x02a0) /* TLB Tag 5 */
! 314: #define EPIC_TLB_TAG_6 (EPIC_BASE + 0x02c0) /* TLB Tag 6 */
! 315: #define EPIC_TLB_TAG_7 (EPIC_BASE + 0x02e0) /* TLB Tag 7 */
! 316: #define EPIC_TLB_TAG_RSVD 0x00000fff
! 317: #define EPIC_TLB_TAG_EVAL 0x00001000
! 318: #define EPIC_TLB_TAG_PCI_PAGE 0xffffe000
! 319:
! 320: #define EPIC_TLB_DATA_0 (EPIC_BASE + 0x0300) /* TLB Data 0 */
! 321: #define EPIC_TLB_DATA_1 (EPIC_BASE + 0x0320) /* TLB Data 1 */
! 322: #define EPIC_TLB_DATA_2 (EPIC_BASE + 0x0340) /* TLB Data 2 */
! 323: #define EPIC_TLB_DATA_3 (EPIC_BASE + 0x0360) /* TLB Data 3 */
! 324: #define EPIC_TLB_DATA_4 (EPIC_BASE + 0x0380) /* TLB Data 4 */
! 325: #define EPIC_TLB_DATA_5 (EPIC_BASE + 0x03a0) /* TLB Data 5 */
! 326: #define EPIC_TLB_DATA_6 (EPIC_BASE + 0x03c0) /* TLB Data 6 */
! 327: #define EPIC_TLB_DATA_7 (EPIC_BASE + 0x03e0) /* TLB Data 7 */
! 328: #define EPIC_TLB_DATA_RSVD 0xffe00001
! 329: #define EPIC_TLB_DATA_CPU_PAGE 0x001ffffe
! 330:
! 331: #define EPIC_TBIA (EPIC_BASE + 0x0400) /* TLB Invl All */
! 332:
! 333: /*
! 334: * EPIC Scatter-Gather Map Entries
! 335: */
! 336:
! 337: struct sgmapent {
! 338: u_int64_t val;
! 339: };
! 340: #define SGMAPENT_EVAL 0x0000000000000001L
! 341: #define SGMAPENT_PFN 0x00000000001ffffeL
! 342: #define SGMAPENT_RSVD 0xffffffffffe00000L
! 343:
! 344: #define SGMAP_MAKEENTRY(pfn) (SGMAPENT_EVAL | ((pfn) << 1))
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