Annotation of sys/arch/alpha/include/sfbreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: sfbreg.h,v 1.4 2003/10/18 20:14:42 jmc Exp $ */
2: /* $NetBSD: sfbreg.h,v 1.1 1996/05/01 21:15:46 cgd Exp $ */
3:
4: /*
5: * Copyright (c) 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: /*
32: * Smart ("CXTurbo") Frame Buffer definitions, from:
33: * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
34: * (DEC order number EK-D3SYS-PM), section 6.
35: *
36: * All definitions are in "dense" TurboChannel space.
37: */
38:
39: /*
40: * Size of the SFB address space.
41: */
42: #define SFB_SIZE 0x1000000
43:
44: /*
45: * Offsets into slot space of each functional unit.
46: */
47: #define SFB_ASIC_OFFSET 0x0100000 /* SFB ASIC Control Registers */
48: #define SFB_ASIC_SIZE 0x0020000
49: #define SFB_RAMDAC_OFFSET 0x01c0000 /* Bt495 RAMDAC Registers */
50: #define SFB_RAMDAC_SIZE 0x0040000
51: #define SFB_FB_OFFSET 0x0200000 /* Frame buffer */
52: #define SFB_FB_SIZE 0x0200000
53: #define SFB_OSBM_OFFSET 0x0600000 /* Off-screen buffer memory */
54: #define SFB_OSBM_SIZE 0x0200000
55:
56: /*
57: * SFB ASIC registers (offsets from SFB_ASIC_OFFSET).
58: */
59: #define SFB_ASIC_COPYBUF_0 0x0000 /* Copy buffer register 0 (R/W) */
60: #define SFB_ASIC_COPYBUF_1 0x0004 /* Copy buffer register 1 (R/W) */
61: #define SFB_ASIC_COPYBUF_2 0x0008 /* Copy buffer register 2 (R/W) */
62: #define SFB_ASIC_COPYBUF_3 0x000c /* Copy buffer register 3 (R/W) */
63: #define SFB_ASIC_COPYBUF_4 0x0010 /* Copy buffer register 4 (R/W) */
64: #define SFB_ASIC_COPYBUF_5 0x0014 /* Copy buffer register 5 (R/W) */
65: #define SFB_ASIC_COPYBUF_6 0x0018 /* Copy buffer register 6 (R/W) */
66: #define SFB_ASIC_COPYBUF_7 0x001c /* Copy buffer register 7 (R/W) */
67: #define SFB_ASIC_FG 0x0020 /* Foreground (R/W) */
68: #define SFB_ASIC_BG 0x0024 /* Background (R/W) */
69: #define SFB_ASIC_PLANEMASK 0x0028 /* PlaneMask (R/W) */
70: #define SFB_ASIC_PIXELMASK 0x002c /* PixelMask (R/W) */
71: #define SFB_ASIC_MODE 0x0030 /* Mode (R/W) */
72: #define SFB_ASIC_ROP 0x0034 /* RasterOp (R/W) */
73: #define SFB_ASIC_PIXELSHIFT 0x0038 /* PixelShift (R/W) */
74: #define SFB_ASIC_ADDRESS 0x003c /* Address (R/W) */
75: #define SFB_ASIC_BRES1 0x0040 /* Bresenham register 1 (R/W) */
76: #define SFB_ASIC_BRES2 0x0044 /* Bresenham register 2 (R/W) */
77: #define SFB_ASIC_BRES3 0x0048 /* Bresenham register 3 (R) (?) */
78: #define SFB_ASIC_BCONT 0x004c /* Bcont (W) */
79: #define SFB_ASIC_DEEP 0x0050 /* Deep (R/W) */
80: #define SFB_ASIC_START 0x0054 /* Start (W) */
81: #define SFB_ASIC_CLEAR_INTR 0x0058 /* Clear Interrupt (W) */
82: #define SFB_ASIC_VIDEO_REFRESH 0x0060 /* Video refresh counter (R/W) */
83: #define SFB_ASIC_VIDEO_HSETUP 0x0064 /* Video horizontal setup (R/W) */
84: #define SFB_ASIC_VIDEO_VSETUP 0x0068 /* Video vertical setup (R/W) */
85: #define SFB_ASIC_VIDEO_BASE 0x006c /* Video base address (R/W) */
86: #define SFB_ASIC_VIDEO_VALID 0x0070 /* Video valid (W) */
87: #define SFB_ASIC_ENABLE_INTR 0x0074 /* Enable/Disable Interrupts (W) */
88: #define SFB_ASIC_TCCLK 0x0078 /* TCCLK count (R/W) */
89: #define SFB_ASIC_VIDCLK 0x007c /* VIDCLK count (R/W) */
90:
91: /*
92: * Bt459 RAMDAC registers (offsets from SFB_RAMDAC_OFFSET)
93: */
94: #define SFB_RAMDAC_ADDRLOW 0x0000 /* Address register low byte */
95: #define SFB_RAMDAC_ADDRHIGH 0x0004 /* Address register high byte */
96: #define SFB_RAMDAC_REGDATA 0x0008 /* Register addressed by addr reg */
97: #define SFB_RAMDAC_CMAPDATA 0x000c /* Colormap loc addressed by addr reg */
CVSweb