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1.1 nbrk 1: /* $OpenBSD: lock.h,v 1.1 2007/04/13 08:31:50 martin Exp $ */
2: /* $NetBSD: lock.h,v 1.16 2001/12/17 23:34:57 thorpej Exp $ */
3:
4: /*-
5: * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: /*
42: * Machine-dependent spin lock operations.
43: */
44:
45: #ifndef _ALPHA_LOCK_H_
46: #define _ALPHA_LOCK_H_
47:
48: typedef __volatile int __cpu_simple_lock_t;
49:
50: #define __SIMPLELOCK_LOCKED 1
51: #define __SIMPLELOCK_UNLOCKED 0
52:
53: static __inline void
54: __cpu_simple_lock_init(__cpu_simple_lock_t *alp)
55: {
56:
57: __asm __volatile(
58: "# BEGIN __cpu_simple_lock_init\n"
59: " stl $31, %0 \n"
60: " mb \n"
61: " # END __cpu_simple_lock_init"
62: : "=m" (*alp));
63: }
64:
65: static __inline void
66: __cpu_simple_lock(__cpu_simple_lock_t *alp)
67: {
68: unsigned long t0;
69:
70: /*
71: * Note, if we detect that the lock is held when
72: * we do the initial load-locked, we spin using
73: * a non-locked load to save the coherency logic
74: * some work.
75: */
76:
77: __asm __volatile(
78: "# BEGIN __cpu_simple_lock\n"
79: "1: ldl_l %0, %3 \n"
80: " bne %0, 2f \n"
81: " bis $31, %2, %0 \n"
82: " stl_c %0, %1 \n"
83: " beq %0, 3f \n"
84: " mb \n"
85: " br 4f \n"
86: "2: ldl %0, %3 \n"
87: " beq %0, 1b \n"
88: " br 2b \n"
89: "3: br 1b \n"
90: "4: \n"
91: " # END __cpu_simple_lock\n"
92: : "=&r" (t0), "=m" (*alp)
93: : "i" (__SIMPLELOCK_LOCKED), "m" (*alp)
94: : "memory");
95: }
96:
97: static __inline int
98: __cpu_simple_lock_try(__cpu_simple_lock_t *alp)
99: {
100: unsigned long t0, v0;
101:
102: __asm __volatile(
103: "# BEGIN __cpu_simple_lock_try\n"
104: "1: ldl_l %0, %4 \n"
105: " bne %0, 2f \n"
106: " bis $31, %3, %0 \n"
107: " stl_c %0, %2 \n"
108: " beq %0, 3f \n"
109: " mb \n"
110: " bis $31, 1, %1 \n"
111: " br 4f \n"
112: "2: bis $31, $31, %1 \n"
113: " br 4f \n"
114: "3: br 1b \n"
115: "4: \n"
116: " # END __cpu_simple_lock_try"
117: : "=&r" (t0), "=r" (v0), "=m" (*alp)
118: : "i" (__SIMPLELOCK_LOCKED), "m" (*alp)
119: : "memory");
120:
121: return (v0 != 0);
122: }
123:
124: static __inline void
125: __cpu_simple_unlock(__cpu_simple_lock_t *alp)
126: {
127:
128: __asm __volatile(
129: "# BEGIN __cpu_simple_unlock\n"
130: " mb \n"
131: " stl $31, %0 \n"
132: " # END __cpu_simple_unlock"
133: : "=m" (*alp));
134: }
135:
136: #if defined(MULTIPROCESSOR)
137: /*
138: * On the Alpha, interprocessor interrupts come in at device priority
139: * level. This can cause some problems while waiting for r/w spinlocks
140: * from a high'ish priority level: IPIs that come in will not be processed.
141: * This can lead to deadlock.
142: *
143: * This hook allows IPIs to be processed while a spinlock's interlock
144: * is released.
145: */
146: #define SPINLOCK_SPIN_HOOK \
147: do { \
148: struct cpu_info *__ci = curcpu(); \
149: int __s; \
150: \
151: if (__ci->ci_ipis != 0) { \
152: /* printf("CPU %lu has IPIs pending\n", \
153: __ci->ci_cpuid); */ \
154: __s = splipi(); \
155: alpha_ipi_process(__ci, NULL); \
156: splx(__s); \
157: } \
158: } while (0)
159: #endif /* MULTIPROCESSOR */
160:
161: #endif /* _ALPHA_LOCK_H_ */