Annotation of sys/arch/alpha/include/alpha_cpu.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: alpha_cpu.h,v 1.8 2002/11/26 01:35:23 art Exp $ */
2: /* $NetBSD: alpha_cpu.h,v 1.43 2001/12/18 04:18:22 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: #ifndef __ALPHA_ALPHA_CPU_H__
32: #define __ALPHA_ALPHA_CPU_H__
33:
34: /*
35: * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
36: *
37: * Definitions for:
38: *
39: * Process Control Block
40: * Interrupt/Exception/Syscall Stack Frame
41: * Processor Status Register
42: * Machine Check Error Summary Register
43: * Machine Check Logout Area
44: * Per CPU state Management of Machine Check Handling
45: * Virtual Memory Management
46: * Kernel Entry Vectors
47: * MMCSR Fault Type Codes
48: * Translation Buffer Invalidation
49: *
50: * and miscellaneous PALcode operations.
51: */
52:
53:
54: /*
55: * Process Control Block definitions [OSF/1 PALcode Specific]
56: */
57:
58: struct alpha_pcb {
59: unsigned long apcb_ksp; /* kernel stack ptr */
60: unsigned long apcb_usp; /* user stack ptr */
61: unsigned long apcb_ptbr; /* page table base reg */
62: unsigned int apcb_cpc; /* charged process cycles */
63: unsigned int apcb_asn; /* address space number */
64: unsigned long apcb_unique; /* process unique value */
65: #define apcb_backup_ksp apcb_unique /* backup kernel stack ptr */
66: unsigned long apcb_flags; /* flags; see below */
67: unsigned long apcb_decrsv0; /* DEC reserved */
68: unsigned long apcb_decrsv1; /* DEC reserved */
69: };
70:
71: #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001
72: #define ALPHA_PCB_FLAGS_PME 0x4000000000000000
73:
74: /*
75: * Interrupt/Exception/Syscall "Hardware" (really PALcode)
76: * Stack Frame definitions
77: *
78: * These are quadword offsets from the sp on kernel entry, i.e.
79: * to get to the value in question you access (sp + (offset * 8)).
80: *
81: * On syscall entry, A0-A2 aren't written to memory but space
82: * _is_ reserved for them.
83: */
84:
85: #define ALPHA_HWFRAME_PS 0 /* processor status register */
86: #define ALPHA_HWFRAME_PC 1 /* program counter */
87: #define ALPHA_HWFRAME_GP 2 /* global pointer */
88: #define ALPHA_HWFRAME_A0 3 /* a0 */
89: #define ALPHA_HWFRAME_A1 4 /* a1 */
90: #define ALPHA_HWFRAME_A2 5 /* a2 */
91:
92: #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */
93:
94: /*
95: * Processor Status Register [OSF/1 PALcode Specific]
96: *
97: * Includes user/kernel mode bit, interrupt priority levels, etc.
98: */
99:
100: #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */
101: #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */
102:
103: #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */
104: #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */
105: #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */
106: #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */
107: #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */
108:
109: #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0
110:
111: /* Convenience constants: what must be set/clear in user mode */
112: #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE
113: #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
114:
115: /*
116: * Interrupt Type Code Definitions [OSF/1 PALcode Specific]
117: */
118:
119: #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */
120: #define ALPHA_INTR_CLOCK 1 /* clock interrupt */
121: #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */
122: #define ALPHA_INTR_DEVICE 3 /* device interrupt */
123: #define ALPHA_INTR_PERF 4 /* performance counter */
124: #define ALPHA_INTR_PASSIVE 5 /* passive release */
125:
126: /*
127: * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
128: *
129: * The following bits are values as read. On write, _PCE, _SCE, and
130: * _MIP are "write 1 to clear."
131: */
132:
133: #define ALPHA_MCES_IMP \
134: 0xffffffff00000000 /* impl. dependent */
135: #define ALPHA_MCES_RSVD \
136: 0x00000000ffffffe0 /* reserved */
137: #define ALPHA_MCES_DSC \
138: 0x0000000000000010 /* disable system correctable error reporting */
139: #define ALPHA_MCES_DPC \
140: 0x0000000000000008 /* disable processor correctable error reporting */
141: #define ALPHA_MCES_PCE \
142: 0x0000000000000004 /* processor correctable error in progress */
143: #define ALPHA_MCES_SCE \
144: 0x0000000000000002 /* system correctable error in progress */
145: #define ALPHA_MCES_MIP \
146: 0x0000000000000001 /* machine check in progress */
147:
148: /*
149: * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
150: *
151: * Note that these are *generic* OSF/1 PALcode specific defines. There are
152: * platform variations to these entities.
153: */
154:
155: struct alpha_logout_area {
156: unsigned int la_frame_size; /* frame size */
157: unsigned int la_flags; /* flags; see below */
158: unsigned int la_cpu_offset; /* offset to cpu area */
159: unsigned int la_system_offset; /* offset to system area */
160: };
161:
162: #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */
163: #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */
164: #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */
165:
166: #define ALPHA_LOGOUT_NOT_BUILT \
167: (struct alpha_logout_area *)0xffffffffffffffff)
168:
169: #define ALPHA_LOGOUT_PAL_AREA(lap) \
170: (unsigned long *)((unsigned char *)(lap) + 16)
171: #define ALPHA_LOGOUT_PAL_SIZE(lap) \
172: ((lap)->la_cpu_offset - 16)
173: #define ALPHA_LOGOUT_CPU_AREA(lap) \
174: (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
175: #define ALPHA_LOGOUT_CPU_SIZE(lap) \
176: ((lap)->la_system_offset - (lap)->la_cpu_offset)
177: #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \
178: (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
179: #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \
180: ((lap)->la_frame_size - (lap)->la_system_offset)
181:
182: /* types of machine checks */
183: #define ALPHA_SYS_ERROR 0x620 /* System correctable error */
184: #define ALPHA_PROC_ERROR 0x630 /* Processor correctable error */
185: #define ALPHA_SYS_MCHECK 0x660 /* System machine check */
186: #define ALPHA_PROC_MCHECK 0x670 /* Processor machine check */
187:
188: /*
189: * Virtual Memory Management definitions [OSF/1 PALcode Specific]
190: *
191: * Includes user and kernel space addresses and information,
192: * page table entry definitions, etc.
193: *
194: * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
195: */
196:
197: #define ALPHA_PGSHIFT 13
198: #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT)
199:
200: #define ALPHA_USEG_BASE 0 /* virtual */
201: #define ALPHA_USEG_END 0x000003ffffffffff
202:
203: #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */
204: #define ALPHA_K0SEG_END 0xfffffdffffffffff
205: #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */
206: #define ALPHA_K1SEG_END 0xffffffffffffffff
207:
208: #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE)
209: #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE)
210:
211: #define ALPHA_PTE_VALID 0x0001UL
212:
213: #define ALPHA_PTE_FAULT_ON_READ 0x0002UL
214: #define ALPHA_PTE_FAULT_ON_WRITE 0x0004UL
215: #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008UL
216:
217: #define ALPHA_PTE_ASM 0x0010UL /* addr. space match */
218: #define ALPHA_PTE_GRANULARITY 0x0060UL /* granularity hint */
219:
220: #define ALPHA_PTE_PROT 0xff00UL
221: #define ALPHA_PTE_KR 0x0100UL
222: #define ALPHA_PTE_UR 0x0200UL
223: #define ALPHA_PTE_KW 0x1000UL
224: #define ALPHA_PTE_UW 0x2000UL
225:
226: #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW)
227:
228: #define ALPHA_PTE_SOFTWARE 0x00000000ffff0000UL
229: #define ALPHA_PTE_PALCODE (~ALPHA_PTE_SOFTWARE) /* shorthand */
230:
231: #define ALPHA_PTE_PFN 0xffffffff00000000UL
232:
233: #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32)
234: #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32)
235:
236: typedef unsigned long alpha_pt_entry_t;
237:
238: /*
239: * Kernel Entry Vectors. [OSF/1 PALcode Specific]
240: */
241:
242: #define ALPHA_KENTRY_INT 0
243: #define ALPHA_KENTRY_ARITH 1
244: #define ALPHA_KENTRY_MM 2
245: #define ALPHA_KENTRY_IF 3
246: #define ALPHA_KENTRY_UNA 4
247: #define ALPHA_KENTRY_SYS 5
248:
249: /*
250: * MMCSR Fault Type Codes. [OSF/1 PALcode Specific]
251: */
252:
253: #define ALPHA_MMCSR_INVALTRANS 0
254: #define ALPHA_MMCSR_ACCESS 1
255: #define ALPHA_MMCSR_FOR 2
256: #define ALPHA_MMCSR_FOE 3
257: #define ALPHA_MMCSR_FOW 4
258:
259: /*
260: * Instruction Fault Type Codes. [OSF/1 PALcode Specific]
261: */
262:
263: #define ALPHA_IF_CODE_BPT 0
264: #define ALPHA_IF_CODE_BUGCHK 1
265: #define ALPHA_IF_CODE_GENTRAP 2
266: #define ALPHA_IF_CODE_FEN 3
267: #define ALPHA_IF_CODE_OPDEC 4
268:
269: #ifdef _KERNEL
270:
271: /*
272: * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
273: */
274:
275: #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */
276: #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */
277: #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */
278: #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */
279: #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */
280:
281: #endif /* _KERNEL */
282:
283: /*
284: * Bits used in the amask instruction [EV56 and later]
285: */
286:
287: #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */
288: #define ALPHA_AMASK_FIX 0x0002 /* floating point conv. ext. */
289: #define ALPHA_AMASK_CIX 0x0004 /* count extension */
290: #define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */
291: #define ALPHA_AMASK_PAT 0x0200 /* precise arith. traps */
292:
293: #define ALPHA_AMASK_ALL (ALPHA_AMASK_BWX|ALPHA_AMASK_FIX| \
294: ALPHA_AMASK_CIX|ALPHA_AMASK_MVI| \
295: ALPHA_AMASK_PAT)
296:
297: #define ALPHA_AMASK_BITS \
298: "\20\12PAT\11MVI\3CIX\2FIX\1BWX"
299:
300: /*
301: * Chip family IDs returned by implver instruction
302: */
303:
304: #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */
305: #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */
306: #define ALPHA_IMPLVER_EV6 2 /* EV6 */
307:
308: #ifdef _KERNEL
309:
310: /*
311: * Maximum processor ID we allow from `whami', and related constants.
312: *
313: * XXX This is not really processor or PALcode specific, but this is
314: * a convenient place to put these definitions.
315: *
316: * XXX This is clipped at 63 so that we can use `long's for proc bitmasks.
317: */
318:
319: #define ALPHA_WHAMI_MAXID 63
320: #define ALPHA_MAXPROCS (ALPHA_WHAMI_MAXID + 1)
321:
322: /*
323: * Misc. support routines.
324: */
325: const char *alpha_dsr_sysname(void);
326:
327: /*
328: * Stubs for Alpha instructions normally inaccessible from C.
329: */
330: unsigned long alpha_amask(unsigned long);
331: unsigned long alpha_implver(void);
332:
333: #endif /* _KERNEL */
334:
335: /* XXX Expose the insn wrappers to userspace, for now. */
336:
337: static __inline unsigned long
338: alpha_rpcc(void)
339: {
340: unsigned long v0;
341:
342: __asm __volatile("rpcc %0" : "=r" (v0));
343: return (v0);
344: }
345:
346: #define alpha_mb() __asm __volatile("mb" : : : "memory")
347: #define alpha_wmb() __asm __volatile("mb" : : : "memory") /* XXX */
348:
349: #if defined(_KERNEL) || defined(_STANDALONE)
350:
351: /*
352: * Stubs for OSF/1 PALcode operations.
353: */
354: #include <machine/pal.h>
355:
356: void alpha_pal_cflush(unsigned long);
357: void alpha_pal_halt(void) __attribute__((__noreturn__));
358: unsigned long _alpha_pal_swpipl(unsigned long); /* for profiling */
359: void alpha_pal_wrent(void *, unsigned long);
360: void alpha_pal_wrvptptr(unsigned long);
361:
362: #define alpha_pal_draina() __asm __volatile("call_pal %0 # PAL_draina" \
363: : : "i" (PAL_draina) : "memory")
364:
365: #define alpha_pal_imb() __asm __volatile("call_pal %0 # PAL_imb" \
366: : : "i" (PAL_imb) : "memory")
367:
368: static __inline unsigned long
369: alpha_pal_rdmces(void)
370: {
371: register unsigned long v0 __asm("$0");
372:
373: __asm __volatile("call_pal %1 # PAL_OSF1_rdmces"
374: : "=r" (v0)
375: : "i" (PAL_OSF1_rdmces)
376: /* clobbers t0, t8..t11 */
377: : "$1", "$22", "$23", "$24", "$25");
378:
379: return (v0);
380: }
381:
382: static __inline unsigned long
383: alpha_pal_rdps(void)
384: {
385: register unsigned long v0 __asm("$0");
386:
387: __asm __volatile("call_pal %1 # PAL_OSF1_rdps"
388: : "=r" (v0)
389: : "i" (PAL_OSF1_rdps)
390: /* clobbers t0, t8..t11 */
391: : "$1", "$22", "$23", "$24", "$25");
392:
393: return (v0);
394: }
395:
396: static __inline unsigned long
397: alpha_pal_rdusp(void)
398: {
399: register unsigned long v0 __asm("$0");
400:
401: __asm __volatile("call_pal %1 # PAL_OSF1_rdusp"
402: : "=r" (v0)
403: : "i" (PAL_OSF1_rdusp)
404: /* clobbers t0, t8..t11 */
405: : "$1", "$22", "$23", "$24", "$25");
406:
407: return (v0);
408: }
409:
410: static __inline unsigned long
411: alpha_pal_rdval(void)
412: {
413: register unsigned long v0 __asm("$0");
414:
415: __asm __volatile("call_pal %1 # PAL_OSF1_rdval"
416: : "=r" (v0)
417: : "i" (PAL_OSF1_rdval)
418: /* clobbers t0, t8..t11 */
419: : "$1", "$22", "$23", "$24", "$25");
420:
421: return (v0);
422: }
423:
424: static __inline unsigned long
425: alpha_pal_swpctx(unsigned long ctx)
426: {
427: register unsigned long a0 __asm("$16") = ctx;
428: register unsigned long v0 __asm("$0");
429:
430: __asm __volatile("call_pal %2 # PAL_OSF1_swpctx"
431: : "=r" (a0), "=r" (v0)
432: : "i" (PAL_OSF1_swpctx), "0" (a0)
433: /* clobbers t0, t8..t11, a0 (above) */
434: : "$1", "$22", "$23", "$24", "$25", "memory");
435:
436: return (v0);
437: }
438:
439: static __inline unsigned long
440: alpha_pal_swpipl(unsigned long ipl)
441: {
442: register unsigned long a0 __asm("$16") = ipl;
443: register unsigned long v0 __asm("$0");
444:
445: __asm __volatile("call_pal %2 # PAL_OSF1_swpipl"
446: : "=r" (a0), "=r" (v0)
447: : "i" (PAL_OSF1_swpipl), "0" (a0)
448: /* clobbers t0, t8..t11, a0 (above) */
449: : "$1", "$22", "$23", "$24", "$25", "memory");
450:
451: return (v0);
452: }
453:
454: static __inline void
455: alpha_pal_tbi(unsigned long op, vaddr_t va)
456: {
457: register unsigned long a0 __asm("$16") = op;
458: register unsigned long a1 __asm("$17") = va;
459:
460: __asm __volatile("call_pal %2 # PAL_OSF1_tbi"
461: : "=r" (a0), "=r" (a1)
462: : "i" (PAL_OSF1_tbi), "0" (a0), "1" (a1)
463: /* clobbers t0, t8..t11, a0 (above), a1 (above) */
464: : "$1", "$22", "$23", "$24", "$25");
465: }
466:
467: static __inline unsigned long
468: alpha_pal_whami(void)
469: {
470: register unsigned long v0 __asm("$0");
471:
472: __asm __volatile("call_pal %1 # PAL_OSF1_whami"
473: : "=r" (v0)
474: : "i" (PAL_OSF1_whami)
475: /* clobbers t0, t8..t11 */
476: : "$1", "$22", "$23", "$24", "$25");
477:
478: return (v0);
479: }
480:
481: static __inline void
482: alpha_pal_wrfen(unsigned long onoff)
483: {
484: register unsigned long a0 __asm("$16") = onoff;
485:
486: __asm __volatile("call_pal %1 # PAL_OSF1_wrfen"
487: : "=r" (a0)
488: : "i" (PAL_OSF1_wrfen), "0" (a0)
489: /* clobbers t0, t8..t11, a0 (above) */
490: : "$1", "$22", "$23", "$24", "$25");
491: }
492:
493: static __inline void
494: alpha_pal_wripir(unsigned long cpu_id)
495: {
496: register unsigned long a0 __asm("$16") = cpu_id;
497:
498: __asm __volatile("call_pal %1 # PAL_ipir"
499: : "=r" (a0)
500: : "i" (PAL_ipir), "0" (a0)
501: /* clobbers t0, t8..t11, a0 (above) */
502: : "$1", "$22", "$23", "$24", "$25");
503: }
504:
505: static __inline void
506: alpha_pal_wrusp(unsigned long usp)
507: {
508: register unsigned long a0 __asm("$16") = usp;
509:
510: __asm __volatile("call_pal %1 # PAL_OSF1_wrusp"
511: : "=r" (a0)
512: : "i" (PAL_OSF1_wrusp), "0" (a0)
513: /* clobbers t0, t8..t11, a0 (above) */
514: : "$1", "$22", "$23", "$24", "$25");
515: }
516:
517: static __inline void
518: alpha_pal_wrmces(unsigned long mces)
519: {
520: register unsigned long a0 __asm("$16") = mces;
521:
522: __asm __volatile("call_pal %1 # PAL_OSF1_wrmces"
523: : "=r" (a0)
524: : "i" (PAL_OSF1_wrmces), "0" (a0)
525: /* clobbers t0, t8..t11 */
526: : "$1", "$22", "$23", "$24", "$25");
527: }
528:
529: static __inline void
530: alpha_pal_wrval(unsigned long val)
531: {
532: register unsigned long a0 __asm("$16") = val;
533:
534: __asm __volatile("call_pal %1 # PAL_OSF1_wrval"
535: : "=r" (a0)
536: : "i" (PAL_OSF1_wrval), "0" (a0)
537: /* clobbers t0, t8..t11, a0 (above) */
538: : "$1", "$22", "$23", "$24", "$25");
539: }
540:
541: #endif /* _KERNEL */
542:
543: #endif /* __ALPHA_ALPHA_CPU_H__ */
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