Annotation of prex-old/sys/arch/i386/pc/interrupt.c, Revision 1.1.1.1
1.1 nbrk 1: /*-
2: * Copyright (c) 2005-2007, Kohsuke Ohtani
3: * All rights reserved.
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: * 3. Neither the name of the author nor the names of any co-contributors
14: * may be used to endorse or promote products derived from this software
15: * without specific prior written permission.
16: *
17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27: * SUCH DAMAGE.
28: */
29:
30: /*
31: * interrupt.c - interrupt handling routines for intel 8259 chip
32: */
33:
34: #include <kernel.h>
35: #include <irq.h>
36: #include <cpu.h>
37:
38: /* I/O address for master/slave programmable interrupt controller */
39: #define PIC_M 0x20
40: #define PIC_S 0xa0
41:
42: /* Edge/level control register */
43: #define ELCR 0x4d0
44:
45: /*
46: * Interrupt priority level
47: *
48: * Each interrupt has its logical priority level, with 0 being the highest
49: * priority. While some ISR is running, all lower priority interrupts
50: * are masked off.
51: */
52: volatile int irq_level;
53:
54: /*
55: * Interrupt mapping table
56: */
57: static int ipl_table[NIRQS]; /* Vector -> level */
58: static u_int mask_table[NIPLS]; /* Level -> mask */
59:
60: /*
61: * Set mask for current ipl
62: */
63: static void
64: update_mask(void)
65: {
66: u_int mask = mask_table[irq_level];
67:
68: outb(mask & 0xff, PIC_M + 1);
69: outb(mask >> 8, PIC_S + 1);
70: }
71:
72: /*
73: * Unmask interrupt in PIC for specified irq.
74: * The interrupt mask table is also updated.
75: * Assumed CPU interrupt is disabled in caller.
76: */
77: void
78: interrupt_unmask(int vector, int level)
79: {
80: int i;
81: u_int unmask = (u_int)~(1 << vector);
82:
83: ipl_table[vector] = level;
84: /*
85: * Unmask target interrupt for all
86: * lower interrupt levels.
87: */
88: for (i = 0; i < level; i++)
89: mask_table[i] &= unmask;
90: update_mask();
91: }
92:
93: /*
94: * Mask interrupt in PIC for specified irq.
95: * Interrupt must be disabled when this routine is called.
96: */
97: void
98: interrupt_mask(int vector)
99: {
100: int i, level;
101: u_int mask = (u_int)(1 << vector);
102:
103: level = ipl_table[vector];
104: for (i = 0; i < level; i++)
105: mask_table[i] |= mask;
106: ipl_table[vector] = IPL_NONE;
107: update_mask();
108: }
109:
110: /*
111: * Setup interrupt mode.
112: * Select whether an interrupt trigger is edge or level.
113: */
114: void
115: interrupt_setup(int vector, int mode)
116: {
117: int port;
118: u_int bit;
119: u_char val;
120:
121: port = vector < 8 ? ELCR : ELCR + 1;
122: bit = (u_int)(1 << (vector & 7));
123:
124: val = inb(port);
125: if (mode == IMODE_LEVEL)
126: val |= bit;
127: else
128: val &= ~bit;
129: outb(val, port);
130: }
131:
132: /*
133: * Common interrupt handler.
134: * This routine is called from low level interrupt routine written
135: * in assemble code. The interrupt flag is automatically disabled
136: * by h/w in CPU when the interrupt is occurred.
137: * The target interrupt will be masked in ICU while the irq handler
138: * is called.
139: */
140: void
141: interrupt_handler(struct cpu_regs *regs)
142: {
143: int vector = (int)regs->trap_no;
144: int old_ipl, new_ipl;
145:
146: /* Adjust interrupt level */
147: old_ipl = irq_level;
148: new_ipl = ipl_table[vector];
149: if (new_ipl > old_ipl) /* Ignore spurious interrupt */
150: irq_level = new_ipl;
151: update_mask();
152:
153: /* Send acknowledge to PIC for specified irq */
154: if (vector & 8) /* Slave ? */
155: outb(0x20, PIC_S); /* Non specific EOI to slave */
156: outb(0x20, PIC_M); /* Non specific EOI to master */
157:
158: /* Dispatch interrupt */
159: sti();
160: irq_handler(vector);
161: cli();
162:
163: /* Restore interrupt level */
164: irq_level = old_ipl;
165: update_mask();
166: }
167:
168: /*
169: * Initialize 8259 interrupt controllers.
170: * All interrupts will be masked off in ICU.
171: */
172: void
173: interrupt_init(void)
174: {
175: int i;
176:
177: irq_level = IPL_NONE;
178:
179: for (i = 0; i < NIRQS; i++)
180: ipl_table[i] = IPL_NONE;
181:
182: for (i = 0; i < NIPLS; i++)
183: mask_table[i] = 0xfffb;
184:
185: outb_p(0x11, PIC_M); /* Start initialization edge, master */
186: outb_p(0x20, PIC_M + 1); /* Set h/w vector = 0x20 */
187: outb_p(0x04, PIC_M + 1); /* Chain to slave (IRQ2) */
188: outb_p(0x01, PIC_M + 1); /* 8086 mode */
189:
190: outb_p(0x11, PIC_S); /* Start initialization edge, master */
191: outb_p(0x28, PIC_S + 1); /* Set h/w vector = 0x28 */
192: outb_p(0x02, PIC_S + 1); /* Slave (cascade) */
193: outb_p(0x01, PIC_S + 1); /* 8086 mode */
194:
195: outb(0xff, PIC_S + 1); /* Mask all */
196: outb(0xfb, PIC_M + 1); /* Mask all except IRQ2 (cascade) */
197: }
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