Annotation of prex-old/sys/arch/arm/cats/clock.c, Revision 1.2
1.1 nbrk 1: /*
1.2 ! nbrk 2: * $Id: clock.c,v 1.1 2008/07/18 20:21:48 nbrk Exp $
1.1 nbrk 3: */
4: /*-
5: * Copyright (c) 2005-2007, Kohsuke Ohtani
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. Neither the name of the author nor the names of any co-contributors
17: * may be used to endorse or promote products derived from this software
18: * without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30: * SUCH DAMAGE.
31: */
32:
33: /*
1.2 ! nbrk 34: * clock.c - SA-110 Operatin System Timer driver.
1.1 nbrk 35: */
36:
37: #include <kernel.h>
38: #include <timer.h>
39: #include <irq.h>
40:
1.2 ! nbrk 41: /*
! 42: * This OST is an incrementing counter running at 3.6864 MHz.
! 43: * It contains four 32-bit Match Registers which can be programmed
! 44: * to cause periodic interrupts in SAIC.
! 45: * For our main clock service we use channel 0.
! 46: */
! 47: #define SAOST_INTRNO 26 /* channel 0 match */
! 48: #define SAOST_FREQ 3686400 /* ticks per second */
! 49:
! 50: #define SAOST_BASE 0x90000000
! 51: #define SAOST_OSMR(x) (x * 4) /* Match Register x */
! 52: #define SAOST_OSCR 0x10
! 53: #define SAOST_OSSR 0x14
! 54: #define SAOST_OIER 0x1c
1.1 nbrk 55:
56: /*
57: * Clock interrupt service routine.
58: * No H/W reprogram is required.
59: */
60: static int
61: clock_isr(int irq)
62: {
63: irq_lock();
1.2 ! nbrk 64:
1.1 nbrk 65: timer_tick();
1.2 ! nbrk 66:
1.1 nbrk 67: irq_unlock();
68:
69: return INT_DONE;
70: }
71:
72: /*
73: * Initialize clock H/W chip.
74: * Setup clock tick rate and install clock ISR.
75: */
76: void
77: clock_init(void)
78: {
1.2 ! nbrk 79: int clock_irq;
! 80:
! 81:
! 82: /* disable interrupts on matching all channels */
! 83: *(volatile uint32_t *)(SAOST_BASE + SAOST_OIER) = 0;
! 84:
! 85: /* set channel 0 to 1/100 / sec */
! 86: *(volatile uint32_t *)(SAOST_BASE + SAOST_OSMR(0)) = SAOST_FREQ / CONFIG_HZ;
! 87:
! 88: clock_irq = irq_attach(SAOST_INTRNO, IPL_CLOCK, 0, clock_isr, NULL);
! 89: ASSERT(clock_irq != -1);
! 90:
! 91: /* enable interrupts on channel 0 compare */
! 92: *(volatile uint32_t *)(SAOST_BASE + SAOST_OIER) = 1;
1.1 nbrk 93: }
1.2 ! nbrk 94:
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