Annotation of prex-old/dev/i386/include/cpu.h, Revision 1.1.1.1
1.1 nbrk 1: /*
2: * Copyright (c) 2005, Kohsuke Ohtani
3: * All rights reserved.
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: * 3. Neither the name of the author nor the names of any co-contributors
14: * may be used to endorse or promote products derived from this software
15: * without specific prior written permission.
16: *
17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27: * SUCH DAMAGE.
28: */
29:
30: #ifndef _CPU_H
31: #define _CPU_H
32:
33: #include <sys/cdefs.h>
34: #include <sys/types.h>
35:
36: #define BREAKPOINT() __asm__ ("int $3"::)
37:
38: /*
39: * I/O instructions
40: */
41: static __inline void
42: outb(unsigned char value, int port)
43: {
44: __asm__ __volatile__(
45: "outb %b0, %w1"
46: ::"a" (value),"Nd" (port));
47: }
48:
49: static __inline void
50: outw(unsigned short value, int port)
51: {
52: __asm__ __volatile__(
53: "outw %w0, %w1"
54: ::"a" (value),"Nd" (port));
55: }
56:
57: static __inline void
58: outl(unsigned long value, int port)
59: {
60: __asm__ __volatile__(
61: "outl %0, %w1"
62: ::"a" (value),"Nd" (port));
63: }
64:
65: static __inline unsigned char
66: inb(int port)
67: {
68: unsigned char _val;
69: __asm__ __volatile__(
70: "inb %w1, %b0"
71: :"=a" (_val)
72: :"Nd" (port));
73: return _val;
74: }
75:
76: static __inline unsigned short
77: inw(int port)
78: {
79: unsigned char _val;
80: __asm__ __volatile__(
81: "inw %w1, %w0"
82: :"=a" (_val)
83: :"Nd" (port));
84: return _val;
85: }
86:
87: static __inline unsigned long
88: inl(int port)
89: {
90: unsigned char _val;
91: __asm__ __volatile__(
92: "inl %w1, %0"
93: :"=a" (_val)
94: :"Nd" (port));
95: return _val;
96: }
97:
98: static __inline void
99: outb_p(unsigned char value, int port)
100: {
101: __asm__ __volatile__(
102: "outb %b0, %w1\n\t"
103: "outb %%al, $0x80\n\t"
104: ::"a" (value),"Nd" (port));
105: }
106:
107: static __inline unsigned char
108: inb_p(int port)
109: {
110: unsigned char _val;
111: __asm__ __volatile__(
112: "inb %w1, %b0\n\t"
113: "outb %%al, $0x80\n\t"
114: :"=a" (_val)
115: :"Nd" (port));
116: return _val;
117: }
118:
119:
120: /*
121: * Macro to read/write the machine specific register (MSR)
122: */
123: #define rdmsr(msr,val1,val2) \
124: __asm__ __volatile__("rdmsr" \
125: : "=a" (val1), "=d" (val2) \
126: : "c" (msr))
127:
128: #define wrmsr(msr,val1,val2) \
129: __asm__ __volatile__("wrmsr" \
130: : /* no outputs */ \
131: : "c" (msr), "a" (val1), "d" (val2))
132:
133: /*
134: * Get cpu id
135: */
136: static __inline void
137: cpuid(u_int eax, u_int *p)
138: {
139: __asm__ __volatile__(
140: "cpuid\n\t"
141: "movl %%eax, 0(%2)\n\t"
142: "movl %%ebx, 4(%2)\n\t"
143: "movl %%ecx, 8(%2)\n\t"
144: "movl %%edx, 12(%2)\n\t"
145: : "=a" (eax)
146: : "0" (eax), "S" (p)
147: : "bx", "cx", "dx");
148: }
149:
150: #endif /* !_CPU_H */
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