version 1.2, 2007/11/04 22:47:16 |
version 1.3, 2007/11/12 13:10:19 |
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#define __cpu_enable_irq() do { __asm __volatile("mrs r0, cpsr\nbic r0, r0, #0x80\nmsr cpsr, r0"); } while(0); |
#define __cpu_enable_irq() do { __asm __volatile("mrs r0, cpsr\nbic r0, r0, #0x80\nmsr cpsr, r0"); } while(0); |
#define __cpu_disable_irq() do { __asm __volatile("mrs r0, cpsr\norr r0, r0, #0x80\nmsr cpsr, r0"); } while(0); |
#define __cpu_disable_irq() do { __asm __volatile("mrs r0, cpsr\norr r0, r0, #0x80\nmsr cpsr, r0"); } while(0); |
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/* |
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* CPU capabilities. |
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*/ |
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/* TODO when CPU identification will work */ |
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#define CPU_HAVE_ICACHE 0x00000001 |
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#define CPU_HAVE_DCACHE 0x00000002 |
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#define CPU_HAVE_MMU 0x00000004 |
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struct cpu_dd { |
struct cpu_dd { |
uint32_t cpu_freq; |
uint32_t cd_dummy; |
char *cpu_name; |
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uint32_t cpu_flags; |
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}; |
}; |
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#endif /* _DEV_CPUVAR_H */ |
#endif /* _DEV_CPUVAR_H */ |