[BACK]Return to saspi.c CVS log [TXT][DIR] Up to [local] / funnyos / arch / sam7s64 / dev

Diff for /funnyos/arch/sam7s64/dev/saspi.c between version 1.3 and 1.4

version 1.3, 2007/12/20 15:25:44 version 1.4, 2007/12/21 17:40:29
Line 23 
Line 23 
 int     saspi_attach(struct device *, uint32_t, uint8_t);  int     saspi_attach(struct device *, uint32_t, uint8_t);
 void    saspi_init(struct saspi_dd *ddp);  void    saspi_init(struct saspi_dd *ddp);
 uint8_t saspi_transmit(void *selfdd, uint8_t data);  uint8_t saspi_transmit(void *selfdd, uint8_t data);
   void    saspi_cs_low(void *selfdd);
   void    saspi_cs_high(void *selfdd);
   
   
 struct driver saspi_dr = {  struct driver saspi_dr = {
Line 68 
Line 70 
         saspi_init(ddp);          saspi_init(ddp);
   
         ddp->sd_sbh.sb_transmitfunc = saspi_transmit;          ddp->sd_sbh.sb_transmitfunc = saspi_transmit;
           ddp->sd_sbh.sb_cslowfunc = saspi_cs_low;
           ddp->sd_sbh.sb_cshighfunc = saspi_cs_high;
         ddp->sd_sbh.sb_dd = ddp;          ddp->sd_sbh.sb_dd = ddp;
   
         self->dv_aux = &ddp->sd_sbh;          self->dv_aux = &ddp->sd_sbh;
Line 97 
Line 101 
         /* assign pins to Peripheral A */          /* assign pins to Peripheral A */
         bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_PIOA_ASR, 1 << 11 | 1 << 12 | 1 << 13 | 1 << 14);          bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_PIOA_ASR, 1 << 11 | 1 << 12 | 1 << 13 | 1 << 14);
   
           bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_PIOA_BSR, 0);
   
         /* reset and enable SPI */          /* reset and enable SPI */
         bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_CR, AT91C_SPI_SPIEN | AT91C_SPI_SWRST);          bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_CR, AT91C_SPI_SPIEN | AT91C_SPI_SWRST);
         /* XXX just to be sure */          /* XXX just to be sure */
         bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_CR, AT91C_SPI_SPIEN);          bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_CR, AT91C_SPI_SPIEN);
   
         /* set SPI mode to master; disable decoding of Chip Select; PCS 1110 (using fixed CS line) */          /* set SPI mode to master; disable decoding of Chip Select; PCS 1110 (using fixed CS line) */
         bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_CR, AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | 0x0e << 16); /* XXX 15|16 */          bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_MR, AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | 0x0e << 16); /* XXX 15|16 */
   //      bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_MR, 0xe0011); /* XXX 15|16 */
   
         /*          /*
          * Configure Chip Select Register no. 0 (so no offset from SPI_CSR).           * Configure Chip Select Register no. 0 (so no offset from SPI_CSR).
Line 136 
Line 143 
         bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_TDR, 0x0000ffff & data);          bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_TDR, 0x0000ffff & data);
   
         /* wait while Receive Register is full and read it */          /* wait while Receive Register is full and read it */
         while((bus_read_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_SR) & AT91C_SPI_RDRF) == 0)          while(((bus_read_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_SR)) & AT91C_SPI_RDRF) == 0)
                 ;                  ;
         return( bus_read_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_RDR) & 0x0000ffff );          return( bus_read_4(ddp->sd_bhp, (uint32_t)AT91C_SPI_RDR) & 0x0000ffff );
   }
   
   
   void
   saspi_cs_low(void *selfdd)
   {
           struct saspi_dd *ddp = selfdd;
           bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_PIOA_CODR, 1 << 11);
   }
   
   
   void
   saspi_cs_high(void *selfdd)
   {
           struct saspi_dd *ddp = selfdd;
           bus_write_4(ddp->sd_bhp, (uint32_t)AT91C_PIOA_SODR, 1 << 11);
   
 }  }
   
Legend:
Removed from v.1.3  
changed lines
  Added in v.1.4
CVSweb