Annotation of funnyos/arch/sam7s64/dev/at91sam7.h, Revision 1.1
1.1 ! nbrk 1: /*
! 2: * $Id: board.h,v 1.2 2007/11/20 19:29:51 nbrk Exp $
! 3: */
! 4: // ----------------------------------------------------------------------------
! 5: // ATMEL Microcontroller Software Support - ROUSSET -
! 6: // ----------------------------------------------------------------------------
! 7: // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
! 8: // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
! 9: // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
! 10: // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
! 11: // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
! 12: // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
! 13: // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
! 14: // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
! 15: // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
! 16: // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 17: // ----------------------------------------------------------------------------
! 18: // File Name : AT91SAM7S64.h
! 19: // Object : AT91SAM7S64 definitions
! 20: // Generated : AT91 SW Application Group 08/30/2005 (15:52:59)
! 21: //
! 22: // CVS Reference : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005//
! 23: // CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
! 24: // CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005//
! 25: // CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
! 26: // CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005//
! 27: // CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005//
! 28: // CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005//
! 29: // CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
! 30: // CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
! 31: // CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
! 32: // CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
! 33: // CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
! 34: // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
! 35: // CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
! 36: // CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
! 37: // CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
! 38: // CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
! 39: // CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
! 40: // CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
! 41: // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
! 42: // CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
! 43: // ----------------------------------------------------------------------------
! 44:
! 45: #ifndef AT91SAM7S64_H
! 46: #define AT91SAM7S64_H
! 47:
! 48: typedef volatile unsigned int AT91_REG;// Hardware register definition
! 49:
! 50: // *****************************************************************************
! 51: // SOFTWARE API DEFINITION FOR System Peripherals
! 52: // *****************************************************************************
! 53: typedef struct _AT91S_SYS {
! 54: AT91_REG AIC_SMR[32]; // Source Mode Register
! 55: AT91_REG AIC_SVR[32]; // Source Vector Register
! 56: AT91_REG AIC_IVR; // IRQ Vector Register
! 57: AT91_REG AIC_FVR; // FIQ Vector Register
! 58: AT91_REG AIC_ISR; // Interrupt Status Register
! 59: AT91_REG AIC_IPR; // Interrupt Pending Register
! 60: AT91_REG AIC_IMR; // Interrupt Mask Register
! 61: AT91_REG AIC_CISR; // Core Interrupt Status Register
! 62: AT91_REG Reserved0[2]; //
! 63: AT91_REG AIC_IECR; // Interrupt Enable Command Register
! 64: AT91_REG AIC_IDCR; // Interrupt Disable Command Register
! 65: AT91_REG AIC_ICCR; // Interrupt Clear Command Register
! 66: AT91_REG AIC_ISCR; // Interrupt Set Command Register
! 67: AT91_REG AIC_EOICR; // End of Interrupt Command Register
! 68: AT91_REG AIC_SPU; // Spurious Vector Register
! 69: AT91_REG AIC_DCR; // Debug Control Register (Protect)
! 70: AT91_REG Reserved1[1]; //
! 71: AT91_REG AIC_FFER; // Fast Forcing Enable Register
! 72: AT91_REG AIC_FFDR; // Fast Forcing Disable Register
! 73: AT91_REG AIC_FFSR; // Fast Forcing Status Register
! 74: AT91_REG Reserved2[45]; //
! 75: AT91_REG DBGU_CR; // Control Register
! 76: AT91_REG DBGU_MR; // Mode Register
! 77: AT91_REG DBGU_IER; // Interrupt Enable Register
! 78: AT91_REG DBGU_IDR; // Interrupt Disable Register
! 79: AT91_REG DBGU_IMR; // Interrupt Mask Register
! 80: AT91_REG DBGU_CSR; // Channel Status Register
! 81: AT91_REG DBGU_RHR; // Receiver Holding Register
! 82: AT91_REG DBGU_THR; // Transmitter Holding Register
! 83: AT91_REG DBGU_BRGR; // Baud Rate Generator Register
! 84: AT91_REG Reserved3[7]; //
! 85: AT91_REG DBGU_CIDR; // Chip ID Register
! 86: AT91_REG DBGU_EXID; // Chip ID Extension Register
! 87: AT91_REG DBGU_FNTR; // Force NTRST Register
! 88: AT91_REG Reserved4[45]; //
! 89: AT91_REG DBGU_RPR; // Receive Pointer Register
! 90: AT91_REG DBGU_RCR; // Receive Counter Register
! 91: AT91_REG DBGU_TPR; // Transmit Pointer Register
! 92: AT91_REG DBGU_TCR; // Transmit Counter Register
! 93: AT91_REG DBGU_RNPR; // Receive Next Pointer Register
! 94: AT91_REG DBGU_RNCR; // Receive Next Counter Register
! 95: AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
! 96: AT91_REG DBGU_TNCR; // Transmit Next Counter Register
! 97: AT91_REG DBGU_PTCR; // PDC Transfer Control Register
! 98: AT91_REG DBGU_PTSR; // PDC Transfer Status Register
! 99: AT91_REG Reserved5[54]; //
! 100: AT91_REG PIOA_PER; // PIO Enable Register
! 101: AT91_REG PIOA_PDR; // PIO Disable Register
! 102: AT91_REG PIOA_PSR; // PIO Status Register
! 103: AT91_REG Reserved6[1]; //
! 104: AT91_REG PIOA_OER; // Output Enable Register
! 105: AT91_REG PIOA_ODR; // Output Disable Registerr
! 106: AT91_REG PIOA_OSR; // Output Status Register
! 107: AT91_REG Reserved7[1]; //
! 108: AT91_REG PIOA_IFER; // Input Filter Enable Register
! 109: AT91_REG PIOA_IFDR; // Input Filter Disable Register
! 110: AT91_REG PIOA_IFSR; // Input Filter Status Register
! 111: AT91_REG Reserved8[1]; //
! 112: AT91_REG PIOA_SODR; // Set Output Data Register
! 113: AT91_REG PIOA_CODR; // Clear Output Data Register
! 114: AT91_REG PIOA_ODSR; // Output Data Status Register
! 115: AT91_REG PIOA_PDSR; // Pin Data Status Register
! 116: AT91_REG PIOA_IER; // Interrupt Enable Register
! 117: AT91_REG PIOA_IDR; // Interrupt Disable Register
! 118: AT91_REG PIOA_IMR; // Interrupt Mask Register
! 119: AT91_REG PIOA_ISR; // Interrupt Status Register
! 120: AT91_REG PIOA_MDER; // Multi-driver Enable Register
! 121: AT91_REG PIOA_MDDR; // Multi-driver Disable Register
! 122: AT91_REG PIOA_MDSR; // Multi-driver Status Register
! 123: AT91_REG Reserved9[1]; //
! 124: AT91_REG PIOA_PPUDR; // Pull-up Disable Register
! 125: AT91_REG PIOA_PPUER; // Pull-up Enable Register
! 126: AT91_REG PIOA_PPUSR; // Pull-up Status Register
! 127: AT91_REG Reserved10[1]; //
! 128: AT91_REG PIOA_ASR; // Select A Register
! 129: AT91_REG PIOA_BSR; // Select B Register
! 130: AT91_REG PIOA_ABSR; // AB Select Status Register
! 131: AT91_REG Reserved11[9]; //
! 132: AT91_REG PIOA_OWER; // Output Write Enable Register
! 133: AT91_REG PIOA_OWDR; // Output Write Disable Register
! 134: AT91_REG PIOA_OWSR; // Output Write Status Register
! 135: AT91_REG Reserved12[469]; //
! 136: AT91_REG PMC_SCER; // System Clock Enable Register
! 137: AT91_REG PMC_SCDR; // System Clock Disable Register
! 138: AT91_REG PMC_SCSR; // System Clock Status Register
! 139: AT91_REG Reserved13[1]; //
! 140: AT91_REG PMC_PCER; // Peripheral Clock Enable Register
! 141: AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
! 142: AT91_REG PMC_PCSR; // Peripheral Clock Status Register
! 143: AT91_REG Reserved14[1]; //
! 144: AT91_REG PMC_MOR; // Main Oscillator Register
! 145: AT91_REG PMC_MCFR; // Main Clock Frequency Register
! 146: AT91_REG Reserved15[1]; //
! 147: AT91_REG PMC_PLLR; // PLL Register
! 148: AT91_REG PMC_MCKR; // Master Clock Register
! 149: AT91_REG Reserved16[3]; //
! 150: AT91_REG PMC_PCKR[3]; // Programmable Clock Register
! 151: AT91_REG Reserved17[5]; //
! 152: AT91_REG PMC_IER; // Interrupt Enable Register
! 153: AT91_REG PMC_IDR; // Interrupt Disable Register
! 154: AT91_REG PMC_SR; // Status Register
! 155: AT91_REG PMC_IMR; // Interrupt Mask Register
! 156: AT91_REG Reserved18[36]; //
! 157: AT91_REG RSTC_RCR; // Reset Control Register
! 158: AT91_REG RSTC_RSR; // Reset Status Register
! 159: AT91_REG RSTC_RMR; // Reset Mode Register
! 160: AT91_REG Reserved19[5]; //
! 161: AT91_REG RTTC_RTMR; // Real-time Mode Register
! 162: AT91_REG RTTC_RTAR; // Real-time Alarm Register
! 163: AT91_REG RTTC_RTVR; // Real-time Value Register
! 164: AT91_REG RTTC_RTSR; // Real-time Status Register
! 165: AT91_REG PITC_PIMR; // Period Interval Mode Register
! 166: AT91_REG PITC_PISR; // Period Interval Status Register
! 167: AT91_REG PITC_PIVR; // Period Interval Value Register
! 168: AT91_REG PITC_PIIR; // Period Interval Image Register
! 169: AT91_REG WDTC_WDCR; // Watchdog Control Register
! 170: AT91_REG WDTC_WDMR; // Watchdog Mode Register
! 171: AT91_REG WDTC_WDSR; // Watchdog Status Register
! 172: AT91_REG Reserved20[5]; //
! 173: AT91_REG VREG_MR; // Voltage Regulator Mode Register
! 174: } AT91S_SYS, *AT91PS_SYS;
! 175:
! 176:
! 177: // *****************************************************************************
! 178: // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
! 179: // *****************************************************************************
! 180: typedef struct _AT91S_AIC {
! 181: AT91_REG AIC_SMR[32]; // Source Mode Register
! 182: AT91_REG AIC_SVR[32]; // Source Vector Register
! 183: AT91_REG AIC_IVR; // IRQ Vector Register
! 184: AT91_REG AIC_FVR; // FIQ Vector Register
! 185: AT91_REG AIC_ISR; // Interrupt Status Register
! 186: AT91_REG AIC_IPR; // Interrupt Pending Register
! 187: AT91_REG AIC_IMR; // Interrupt Mask Register
! 188: AT91_REG AIC_CISR; // Core Interrupt Status Register
! 189: AT91_REG Reserved0[2]; //
! 190: AT91_REG AIC_IECR; // Interrupt Enable Command Register
! 191: AT91_REG AIC_IDCR; // Interrupt Disable Command Register
! 192: AT91_REG AIC_ICCR; // Interrupt Clear Command Register
! 193: AT91_REG AIC_ISCR; // Interrupt Set Command Register
! 194: AT91_REG AIC_EOICR; // End of Interrupt Command Register
! 195: AT91_REG AIC_SPU; // Spurious Vector Register
! 196: AT91_REG AIC_DCR; // Debug Control Register (Protect)
! 197: AT91_REG Reserved1[1]; //
! 198: AT91_REG AIC_FFER; // Fast Forcing Enable Register
! 199: AT91_REG AIC_FFDR; // Fast Forcing Disable Register
! 200: AT91_REG AIC_FFSR; // Fast Forcing Status Register
! 201: } AT91S_AIC, *AT91PS_AIC;
! 202:
! 203: // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
! 204: #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
! 205: #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
! 206: #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
! 207: #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
! 208: #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
! 209: #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
! 210: #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
! 211: #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
! 212: #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
! 213: #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
! 214: // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
! 215: #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
! 216: #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
! 217: // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
! 218: #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
! 219: #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
! 220:
! 221: // *****************************************************************************
! 222: // SOFTWARE API DEFINITION FOR Peripheral DMA Controller
! 223: // *****************************************************************************
! 224: typedef struct _AT91S_PDC {
! 225: AT91_REG PDC_RPR; // Receive Pointer Register
! 226: AT91_REG PDC_RCR; // Receive Counter Register
! 227: AT91_REG PDC_TPR; // Transmit Pointer Register
! 228: AT91_REG PDC_TCR; // Transmit Counter Register
! 229: AT91_REG PDC_RNPR; // Receive Next Pointer Register
! 230: AT91_REG PDC_RNCR; // Receive Next Counter Register
! 231: AT91_REG PDC_TNPR; // Transmit Next Pointer Register
! 232: AT91_REG PDC_TNCR; // Transmit Next Counter Register
! 233: AT91_REG PDC_PTCR; // PDC Transfer Control Register
! 234: AT91_REG PDC_PTSR; // PDC Transfer Status Register
! 235: } AT91S_PDC, *AT91PS_PDC;
! 236:
! 237: // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
! 238: #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
! 239: #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
! 240: #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
! 241: #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
! 242: // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
! 243:
! 244: // *****************************************************************************
! 245: // SOFTWARE API DEFINITION FOR Debug Unit
! 246: // *****************************************************************************
! 247: typedef struct _AT91S_DBGU {
! 248: AT91_REG DBGU_CR; // Control Register
! 249: AT91_REG DBGU_MR; // Mode Register
! 250: AT91_REG DBGU_IER; // Interrupt Enable Register
! 251: AT91_REG DBGU_IDR; // Interrupt Disable Register
! 252: AT91_REG DBGU_IMR; // Interrupt Mask Register
! 253: AT91_REG DBGU_CSR; // Channel Status Register
! 254: AT91_REG DBGU_RHR; // Receiver Holding Register
! 255: AT91_REG DBGU_THR; // Transmitter Holding Register
! 256: AT91_REG DBGU_BRGR; // Baud Rate Generator Register
! 257: AT91_REG Reserved0[7]; //
! 258: AT91_REG DBGU_CIDR; // Chip ID Register
! 259: AT91_REG DBGU_EXID; // Chip ID Extension Register
! 260: AT91_REG DBGU_FNTR; // Force NTRST Register
! 261: AT91_REG Reserved1[45]; //
! 262: AT91_REG DBGU_RPR; // Receive Pointer Register
! 263: AT91_REG DBGU_RCR; // Receive Counter Register
! 264: AT91_REG DBGU_TPR; // Transmit Pointer Register
! 265: AT91_REG DBGU_TCR; // Transmit Counter Register
! 266: AT91_REG DBGU_RNPR; // Receive Next Pointer Register
! 267: AT91_REG DBGU_RNCR; // Receive Next Counter Register
! 268: AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
! 269: AT91_REG DBGU_TNCR; // Transmit Next Counter Register
! 270: AT91_REG DBGU_PTCR; // PDC Transfer Control Register
! 271: AT91_REG DBGU_PTSR; // PDC Transfer Status Register
! 272: } AT91S_DBGU, *AT91PS_DBGU;
! 273:
! 274: // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
! 275: #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
! 276: #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
! 277: #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
! 278: #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
! 279: #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
! 280: #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
! 281: #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
! 282: // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
! 283: #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
! 284: #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
! 285: #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
! 286: #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
! 287: #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
! 288: #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
! 289: #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
! 290: #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
! 291: #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
! 292: #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
! 293: #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
! 294: #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
! 295: // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
! 296: #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
! 297: #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
! 298: #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
! 299: #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
! 300: #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
! 301: #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
! 302: #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
! 303: #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
! 304: #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
! 305: #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
! 306: #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
! 307: #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
! 308: // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
! 309: // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
! 310: // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
! 311: // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
! 312: #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
! 313:
! 314: // *****************************************************************************
! 315: // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
! 316: // *****************************************************************************
! 317: typedef struct _AT91S_PIO {
! 318: AT91_REG PIO_PER; // PIO Enable Register
! 319: AT91_REG PIO_PDR; // PIO Disable Register
! 320: AT91_REG PIO_PSR; // PIO Status Register
! 321: AT91_REG Reserved0[1]; //
! 322: AT91_REG PIO_OER; // Output Enable Register
! 323: AT91_REG PIO_ODR; // Output Disable Registerr
! 324: AT91_REG PIO_OSR; // Output Status Register
! 325: AT91_REG Reserved1[1]; //
! 326: AT91_REG PIO_IFER; // Input Filter Enable Register
! 327: AT91_REG PIO_IFDR; // Input Filter Disable Register
! 328: AT91_REG PIO_IFSR; // Input Filter Status Register
! 329: AT91_REG Reserved2[1]; //
! 330: AT91_REG PIO_SODR; // Set Output Data Register
! 331: AT91_REG PIO_CODR; // Clear Output Data Register
! 332: AT91_REG PIO_ODSR; // Output Data Status Register
! 333: AT91_REG PIO_PDSR; // Pin Data Status Register
! 334: AT91_REG PIO_IER; // Interrupt Enable Register
! 335: AT91_REG PIO_IDR; // Interrupt Disable Register
! 336: AT91_REG PIO_IMR; // Interrupt Mask Register
! 337: AT91_REG PIO_ISR; // Interrupt Status Register
! 338: AT91_REG PIO_MDER; // Multi-driver Enable Register
! 339: AT91_REG PIO_MDDR; // Multi-driver Disable Register
! 340: AT91_REG PIO_MDSR; // Multi-driver Status Register
! 341: AT91_REG Reserved3[1]; //
! 342: AT91_REG PIO_PPUDR; // Pull-up Disable Register
! 343: AT91_REG PIO_PPUER; // Pull-up Enable Register
! 344: AT91_REG PIO_PPUSR; // Pull-up Status Register
! 345: AT91_REG Reserved4[1]; //
! 346: AT91_REG PIO_ASR; // Select A Register
! 347: AT91_REG PIO_BSR; // Select B Register
! 348: AT91_REG PIO_ABSR; // AB Select Status Register
! 349: AT91_REG Reserved5[9]; //
! 350: AT91_REG PIO_OWER; // Output Write Enable Register
! 351: AT91_REG PIO_OWDR; // Output Write Disable Register
! 352: AT91_REG PIO_OWSR; // Output Write Status Register
! 353: } AT91S_PIO, *AT91PS_PIO;
! 354:
! 355:
! 356: // *****************************************************************************
! 357: // SOFTWARE API DEFINITION FOR Clock Generator Controler
! 358: // *****************************************************************************
! 359: typedef struct _AT91S_CKGR {
! 360: AT91_REG CKGR_MOR; // Main Oscillator Register
! 361: AT91_REG CKGR_MCFR; // Main Clock Frequency Register
! 362: AT91_REG Reserved0[1]; //
! 363: AT91_REG CKGR_PLLR; // PLL Register
! 364: } AT91S_CKGR, *AT91PS_CKGR;
! 365:
! 366: // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
! 367: #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
! 368: #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
! 369: #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
! 370: // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
! 371: #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
! 372: #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
! 373: // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
! 374: #define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
! 375: #define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
! 376: #define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
! 377: #define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
! 378: #define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
! 379: #define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
! 380: #define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
! 381: #define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
! 382: #define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
! 383: #define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
! 384: #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
! 385: #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
! 386: #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
! 387: #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
! 388:
! 389: // *****************************************************************************
! 390: // SOFTWARE API DEFINITION FOR Power Management Controler
! 391: // *****************************************************************************
! 392: typedef struct _AT91S_PMC {
! 393: AT91_REG PMC_SCER; // System Clock Enable Register
! 394: AT91_REG PMC_SCDR; // System Clock Disable Register
! 395: AT91_REG PMC_SCSR; // System Clock Status Register
! 396: AT91_REG Reserved0[1]; //
! 397: AT91_REG PMC_PCER; // Peripheral Clock Enable Register
! 398: AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
! 399: AT91_REG PMC_PCSR; // Peripheral Clock Status Register
! 400: AT91_REG Reserved1[1]; //
! 401: AT91_REG PMC_MOR; // Main Oscillator Register
! 402: AT91_REG PMC_MCFR; // Main Clock Frequency Register
! 403: AT91_REG Reserved2[1]; //
! 404: AT91_REG PMC_PLLR; // PLL Register
! 405: AT91_REG PMC_MCKR; // Master Clock Register
! 406: AT91_REG Reserved3[3]; //
! 407: AT91_REG PMC_PCKR[3]; // Programmable Clock Register
! 408: AT91_REG Reserved4[5]; //
! 409: AT91_REG PMC_IER; // Interrupt Enable Register
! 410: AT91_REG PMC_IDR; // Interrupt Disable Register
! 411: AT91_REG PMC_SR; // Status Register
! 412: AT91_REG PMC_IMR; // Interrupt Mask Register
! 413: } AT91S_PMC, *AT91PS_PMC;
! 414:
! 415: // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
! 416: #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
! 417: #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
! 418: #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
! 419: #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
! 420: #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
! 421: // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
! 422: // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
! 423: // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
! 424: // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
! 425: // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
! 426: // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
! 427: #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
! 428: #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
! 429: #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
! 430: #define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
! 431: #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
! 432: #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
! 433: #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
! 434: #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
! 435: #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
! 436: #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
! 437: #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
! 438: #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
! 439: // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
! 440: // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
! 441: #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
! 442: #define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
! 443: #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
! 444: #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
! 445: #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
! 446: #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
! 447: // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
! 448: // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
! 449: // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
! 450:
! 451: // *****************************************************************************
! 452: // SOFTWARE API DEFINITION FOR Reset Controller Interface
! 453: // *****************************************************************************
! 454: typedef struct _AT91S_RSTC {
! 455: AT91_REG RSTC_RCR; // Reset Control Register
! 456: AT91_REG RSTC_RSR; // Reset Status Register
! 457: AT91_REG RSTC_RMR; // Reset Mode Register
! 458: } AT91S_RSTC, *AT91PS_RSTC;
! 459:
! 460: // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
! 461: #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
! 462: #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
! 463: #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
! 464: #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
! 465: // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
! 466: #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
! 467: #define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
! 468: #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
! 469: #define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
! 470: #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
! 471: #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
! 472: #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
! 473: #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
! 474: #define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
! 475: #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
! 476: #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
! 477: // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
! 478: #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
! 479: #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
! 480: #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length
! 481: #define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
! 482:
! 483: // *****************************************************************************
! 484: // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
! 485: // *****************************************************************************
! 486: typedef struct _AT91S_RTTC {
! 487: AT91_REG RTTC_RTMR; // Real-time Mode Register
! 488: AT91_REG RTTC_RTAR; // Real-time Alarm Register
! 489: AT91_REG RTTC_RTVR; // Real-time Value Register
! 490: AT91_REG RTTC_RTSR; // Real-time Status Register
! 491: } AT91S_RTTC, *AT91PS_RTTC;
! 492:
! 493: // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
! 494: #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
! 495: #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
! 496: #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
! 497: #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
! 498: // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
! 499: #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
! 500: // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
! 501: #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
! 502: // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
! 503: #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
! 504: #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
! 505:
! 506: // *****************************************************************************
! 507: // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
! 508: // *****************************************************************************
! 509: typedef struct _AT91S_PITC {
! 510: AT91_REG PITC_PIMR; // Period Interval Mode Register
! 511: AT91_REG PITC_PISR; // Period Interval Status Register
! 512: AT91_REG PITC_PIVR; // Period Interval Value Register
! 513: AT91_REG PITC_PIIR; // Period Interval Image Register
! 514: } AT91S_PITC, *AT91PS_PITC;
! 515:
! 516: // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
! 517: #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
! 518: #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
! 519: #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
! 520: // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
! 521: #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
! 522: // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
! 523: #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
! 524: #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
! 525: // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
! 526:
! 527: // *****************************************************************************
! 528: // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
! 529: // *****************************************************************************
! 530: typedef struct _AT91S_WDTC {
! 531: AT91_REG WDTC_WDCR; // Watchdog Control Register
! 532: AT91_REG WDTC_WDMR; // Watchdog Mode Register
! 533: AT91_REG WDTC_WDSR; // Watchdog Status Register
! 534: } AT91S_WDTC, *AT91PS_WDTC;
! 535:
! 536: // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
! 537: #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
! 538: #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
! 539: // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
! 540: #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
! 541: #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
! 542: #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
! 543: #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
! 544: #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
! 545: #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
! 546: #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
! 547: #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
! 548: // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
! 549: #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
! 550: #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
! 551:
! 552: // *****************************************************************************
! 553: // SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
! 554: // *****************************************************************************
! 555: typedef struct _AT91S_VREG {
! 556: AT91_REG VREG_MR; // Voltage Regulator Mode Register
! 557: } AT91S_VREG, *AT91PS_VREG;
! 558:
! 559: // -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
! 560: #define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
! 561:
! 562: // *****************************************************************************
! 563: // SOFTWARE API DEFINITION FOR Memory Controller Interface
! 564: // *****************************************************************************
! 565: typedef struct _AT91S_MC {
! 566: AT91_REG MC_RCR; // MC Remap Control Register
! 567: AT91_REG MC_ASR; // MC Abort Status Register
! 568: AT91_REG MC_AASR; // MC Abort Address Status Register
! 569: AT91_REG Reserved0[21]; //
! 570: AT91_REG MC_FMR; // MC Flash Mode Register
! 571: AT91_REG MC_FCR; // MC Flash Command Register
! 572: AT91_REG MC_FSR; // MC Flash Status Register
! 573: } AT91S_MC, *AT91PS_MC;
! 574:
! 575: // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
! 576: #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
! 577: // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
! 578: #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
! 579: #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
! 580: #define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
! 581: #define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
! 582: #define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
! 583: #define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
! 584: #define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
! 585: #define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
! 586: #define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
! 587: #define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
! 588: #define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
! 589: #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
! 590: #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
! 591: #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
! 592: // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
! 593: #define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
! 594: #define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
! 595: #define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
! 596: #define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
! 597: #define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
! 598: #define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
! 599: #define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
! 600: #define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
! 601: #define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
! 602: #define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
! 603: // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
! 604: #define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
! 605: #define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
! 606: #define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
! 607: #define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
! 608: #define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
! 609: #define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
! 610: #define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
! 611: #define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
! 612: #define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
! 613: #define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
! 614: #define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
! 615: // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
! 616: #define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
! 617: #define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
! 618: #define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
! 619: #define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
! 620: #define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
! 621: #define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
! 622: #define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
! 623: #define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
! 624: #define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
! 625: #define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
! 626: #define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
! 627: #define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
! 628: #define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
! 629: #define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
! 630: #define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
! 631: #define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
! 632: #define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
! 633: #define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
! 634: #define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
! 635: #define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
! 636: #define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
! 637: #define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
! 638: #define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
! 639: #define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
! 640: #define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
! 641:
! 642: // *****************************************************************************
! 643: // SOFTWARE API DEFINITION FOR Serial Parallel Interface
! 644: // *****************************************************************************
! 645: typedef struct _AT91S_SPI {
! 646: AT91_REG SPI_CR; // Control Register
! 647: AT91_REG SPI_MR; // Mode Register
! 648: AT91_REG SPI_RDR; // Receive Data Register
! 649: AT91_REG SPI_TDR; // Transmit Data Register
! 650: AT91_REG SPI_SR; // Status Register
! 651: AT91_REG SPI_IER; // Interrupt Enable Register
! 652: AT91_REG SPI_IDR; // Interrupt Disable Register
! 653: AT91_REG SPI_IMR; // Interrupt Mask Register
! 654: AT91_REG Reserved0[4]; //
! 655: AT91_REG SPI_CSR[4]; // Chip Select Register
! 656: AT91_REG Reserved1[48]; //
! 657: AT91_REG SPI_RPR; // Receive Pointer Register
! 658: AT91_REG SPI_RCR; // Receive Counter Register
! 659: AT91_REG SPI_TPR; // Transmit Pointer Register
! 660: AT91_REG SPI_TCR; // Transmit Counter Register
! 661: AT91_REG SPI_RNPR; // Receive Next Pointer Register
! 662: AT91_REG SPI_RNCR; // Receive Next Counter Register
! 663: AT91_REG SPI_TNPR; // Transmit Next Pointer Register
! 664: AT91_REG SPI_TNCR; // Transmit Next Counter Register
! 665: AT91_REG SPI_PTCR; // PDC Transfer Control Register
! 666: AT91_REG SPI_PTSR; // PDC Transfer Status Register
! 667: } AT91S_SPI, *AT91PS_SPI;
! 668:
! 669: // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
! 670: #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
! 671: #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
! 672: #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
! 673: #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
! 674: // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
! 675: #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
! 676: #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
! 677: #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
! 678: #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
! 679: #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
! 680: #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
! 681: #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
! 682: #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
! 683: #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
! 684: #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
! 685: // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
! 686: #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
! 687: #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
! 688: // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
! 689: #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
! 690: #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
! 691: // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
! 692: #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
! 693: #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
! 694: #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
! 695: #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
! 696: #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
! 697: #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
! 698: #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
! 699: #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
! 700: #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
! 701: #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
! 702: #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
! 703: // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
! 704: // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
! 705: // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
! 706: // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
! 707: #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
! 708: #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
! 709: #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
! 710: #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
! 711: #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
! 712: #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
! 713: #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
! 714: #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
! 715: #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
! 716: #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
! 717: #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
! 718: #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
! 719: #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
! 720: #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
! 721: #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
! 722: #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
! 723:
! 724: // *****************************************************************************
! 725: // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
! 726: // *****************************************************************************
! 727: typedef struct _AT91S_ADC {
! 728: AT91_REG ADC_CR; // ADC Control Register
! 729: AT91_REG ADC_MR; // ADC Mode Register
! 730: AT91_REG Reserved0[2]; //
! 731: AT91_REG ADC_CHER; // ADC Channel Enable Register
! 732: AT91_REG ADC_CHDR; // ADC Channel Disable Register
! 733: AT91_REG ADC_CHSR; // ADC Channel Status Register
! 734: AT91_REG ADC_SR; // ADC Status Register
! 735: AT91_REG ADC_LCDR; // ADC Last Converted Data Register
! 736: AT91_REG ADC_IER; // ADC Interrupt Enable Register
! 737: AT91_REG ADC_IDR; // ADC Interrupt Disable Register
! 738: AT91_REG ADC_IMR; // ADC Interrupt Mask Register
! 739: AT91_REG ADC_CDR0; // ADC Channel Data Register 0
! 740: AT91_REG ADC_CDR1; // ADC Channel Data Register 1
! 741: AT91_REG ADC_CDR2; // ADC Channel Data Register 2
! 742: AT91_REG ADC_CDR3; // ADC Channel Data Register 3
! 743: AT91_REG ADC_CDR4; // ADC Channel Data Register 4
! 744: AT91_REG ADC_CDR5; // ADC Channel Data Register 5
! 745: AT91_REG ADC_CDR6; // ADC Channel Data Register 6
! 746: AT91_REG ADC_CDR7; // ADC Channel Data Register 7
! 747: AT91_REG Reserved1[44]; //
! 748: AT91_REG ADC_RPR; // Receive Pointer Register
! 749: AT91_REG ADC_RCR; // Receive Counter Register
! 750: AT91_REG ADC_TPR; // Transmit Pointer Register
! 751: AT91_REG ADC_TCR; // Transmit Counter Register
! 752: AT91_REG ADC_RNPR; // Receive Next Pointer Register
! 753: AT91_REG ADC_RNCR; // Receive Next Counter Register
! 754: AT91_REG ADC_TNPR; // Transmit Next Pointer Register
! 755: AT91_REG ADC_TNCR; // Transmit Next Counter Register
! 756: AT91_REG ADC_PTCR; // PDC Transfer Control Register
! 757: AT91_REG ADC_PTSR; // PDC Transfer Status Register
! 758: } AT91S_ADC, *AT91PS_ADC;
! 759:
! 760: // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
! 761: #define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
! 762: #define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
! 763: // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
! 764: #define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
! 765: #define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
! 766: #define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
! 767: #define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
! 768: #define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
! 769: #define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
! 770: #define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
! 771: #define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
! 772: #define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
! 773: #define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
! 774: #define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
! 775: #define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
! 776: #define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
! 777: #define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
! 778: #define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
! 779: #define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
! 780: #define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
! 781: #define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
! 782: #define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
! 783: #define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
! 784: // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
! 785: #define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
! 786: #define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
! 787: #define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
! 788: #define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
! 789: #define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
! 790: #define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
! 791: #define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
! 792: #define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
! 793: // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
! 794: // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
! 795: // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
! 796: #define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
! 797: #define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
! 798: #define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
! 799: #define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
! 800: #define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
! 801: #define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
! 802: #define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
! 803: #define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
! 804: #define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
! 805: #define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
! 806: #define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
! 807: #define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
! 808: #define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
! 809: #define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
! 810: #define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
! 811: #define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
! 812: #define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
! 813: #define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
! 814: #define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
! 815: #define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
! 816: // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
! 817: #define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
! 818: // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
! 819: // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
! 820: // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
! 821: // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
! 822: #define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
! 823: // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
! 824: // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
! 825: // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
! 826: // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
! 827: // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
! 828: // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
! 829: // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
! 830:
! 831: // *****************************************************************************
! 832: // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
! 833: // *****************************************************************************
! 834: typedef struct _AT91S_SSC {
! 835: AT91_REG SSC_CR; // Control Register
! 836: AT91_REG SSC_CMR; // Clock Mode Register
! 837: AT91_REG Reserved0[2]; //
! 838: AT91_REG SSC_RCMR; // Receive Clock ModeRegister
! 839: AT91_REG SSC_RFMR; // Receive Frame Mode Register
! 840: AT91_REG SSC_TCMR; // Transmit Clock Mode Register
! 841: AT91_REG SSC_TFMR; // Transmit Frame Mode Register
! 842: AT91_REG SSC_RHR; // Receive Holding Register
! 843: AT91_REG SSC_THR; // Transmit Holding Register
! 844: AT91_REG Reserved1[2]; //
! 845: AT91_REG SSC_RSHR; // Receive Sync Holding Register
! 846: AT91_REG SSC_TSHR; // Transmit Sync Holding Register
! 847: AT91_REG Reserved2[2]; //
! 848: AT91_REG SSC_SR; // Status Register
! 849: AT91_REG SSC_IER; // Interrupt Enable Register
! 850: AT91_REG SSC_IDR; // Interrupt Disable Register
! 851: AT91_REG SSC_IMR; // Interrupt Mask Register
! 852: AT91_REG Reserved3[44]; //
! 853: AT91_REG SSC_RPR; // Receive Pointer Register
! 854: AT91_REG SSC_RCR; // Receive Counter Register
! 855: AT91_REG SSC_TPR; // Transmit Pointer Register
! 856: AT91_REG SSC_TCR; // Transmit Counter Register
! 857: AT91_REG SSC_RNPR; // Receive Next Pointer Register
! 858: AT91_REG SSC_RNCR; // Receive Next Counter Register
! 859: AT91_REG SSC_TNPR; // Transmit Next Pointer Register
! 860: AT91_REG SSC_TNCR; // Transmit Next Counter Register
! 861: AT91_REG SSC_PTCR; // PDC Transfer Control Register
! 862: AT91_REG SSC_PTSR; // PDC Transfer Status Register
! 863: } AT91S_SSC, *AT91PS_SSC;
! 864:
! 865: // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
! 866: #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
! 867: #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
! 868: #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
! 869: #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
! 870: #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
! 871: // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
! 872: #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
! 873: #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
! 874: #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
! 875: #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
! 876: #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
! 877: #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
! 878: #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
! 879: #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
! 880: #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
! 881: #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
! 882: #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
! 883: #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
! 884: #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
! 885: #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
! 886: #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
! 887: #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
! 888: #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
! 889: #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
! 890: #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
! 891: #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
! 892: #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
! 893: // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
! 894: #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
! 895: #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
! 896: #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
! 897: #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
! 898: #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
! 899: #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
! 900: #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
! 901: #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
! 902: #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
! 903: #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
! 904: #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
! 905: #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
! 906: #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
! 907: // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
! 908: // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
! 909: #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
! 910: #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
! 911: // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
! 912: #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
! 913: #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
! 914: #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
! 915: #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
! 916: #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
! 917: #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
! 918: #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
! 919: #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
! 920: #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
! 921: #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
! 922: #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
! 923: #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
! 924: // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
! 925: // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
! 926: // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
! 927:
! 928: // *****************************************************************************
! 929: // SOFTWARE API DEFINITION FOR Usart
! 930: // *****************************************************************************
! 931: typedef struct _AT91S_USART {
! 932: AT91_REG US_CR; // Control Register
! 933: AT91_REG US_MR; // Mode Register
! 934: AT91_REG US_IER; // Interrupt Enable Register
! 935: AT91_REG US_IDR; // Interrupt Disable Register
! 936: AT91_REG US_IMR; // Interrupt Mask Register
! 937: AT91_REG US_CSR; // Channel Status Register
! 938: AT91_REG US_RHR; // Receiver Holding Register
! 939: AT91_REG US_THR; // Transmitter Holding Register
! 940: AT91_REG US_BRGR; // Baud Rate Generator Register
! 941: AT91_REG US_RTOR; // Receiver Time-out Register
! 942: AT91_REG US_TTGR; // Transmitter Time-guard Register
! 943: AT91_REG Reserved0[5]; //
! 944: AT91_REG US_FIDI; // FI_DI_Ratio Register
! 945: AT91_REG US_NER; // Nb Errors Register
! 946: AT91_REG Reserved1[1]; //
! 947: AT91_REG US_IF; // IRDA_FILTER Register
! 948: AT91_REG Reserved2[44]; //
! 949: AT91_REG US_RPR; // Receive Pointer Register
! 950: AT91_REG US_RCR; // Receive Counter Register
! 951: AT91_REG US_TPR; // Transmit Pointer Register
! 952: AT91_REG US_TCR; // Transmit Counter Register
! 953: AT91_REG US_RNPR; // Receive Next Pointer Register
! 954: AT91_REG US_RNCR; // Receive Next Counter Register
! 955: AT91_REG US_TNPR; // Transmit Next Pointer Register
! 956: AT91_REG US_TNCR; // Transmit Next Counter Register
! 957: AT91_REG US_PTCR; // PDC Transfer Control Register
! 958: AT91_REG US_PTSR; // PDC Transfer Status Register
! 959: } AT91S_USART, *AT91PS_USART;
! 960:
! 961: // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
! 962: #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
! 963: #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
! 964: #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
! 965: #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
! 966: #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
! 967: #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
! 968: #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
! 969: #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
! 970: #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
! 971: #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
! 972: #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
! 973: // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
! 974: #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
! 975: #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
! 976: #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
! 977: #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
! 978: #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
! 979: #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
! 980: #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
! 981: #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
! 982: #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
! 983: #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
! 984: #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
! 985: #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
! 986: #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
! 987: #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
! 988: #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
! 989: #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
! 990: #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
! 991: #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
! 992: #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
! 993: #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
! 994: #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
! 995: #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
! 996: #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
! 997: #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
! 998: #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
! 999: #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
! 1000: #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
! 1001: #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
! 1002: #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
! 1003: #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
! 1004: #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
! 1005: #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
! 1006: // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
! 1007: #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
! 1008: #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
! 1009: #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
! 1010: #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
! 1011: #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
! 1012: #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
! 1013: #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
! 1014: #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
! 1015: // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
! 1016: // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
! 1017: // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
! 1018: #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
! 1019: #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
! 1020: #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
! 1021: #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
! 1022:
! 1023: // *****************************************************************************
! 1024: // SOFTWARE API DEFINITION FOR Two-wire Interface
! 1025: // *****************************************************************************
! 1026: typedef struct _AT91S_TWI {
! 1027: AT91_REG TWI_CR; // Control Register
! 1028: AT91_REG TWI_MMR; // Master Mode Register
! 1029: AT91_REG Reserved0[1]; //
! 1030: AT91_REG TWI_IADR; // Internal Address Register
! 1031: AT91_REG TWI_CWGR; // Clock Waveform Generator Register
! 1032: AT91_REG Reserved1[3]; //
! 1033: AT91_REG TWI_SR; // Status Register
! 1034: AT91_REG TWI_IER; // Interrupt Enable Register
! 1035: AT91_REG TWI_IDR; // Interrupt Disable Register
! 1036: AT91_REG TWI_IMR; // Interrupt Mask Register
! 1037: AT91_REG TWI_RHR; // Receive Holding Register
! 1038: AT91_REG TWI_THR; // Transmit Holding Register
! 1039: } AT91S_TWI, *AT91PS_TWI;
! 1040:
! 1041: // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
! 1042: #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
! 1043: #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
! 1044: #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
! 1045: #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
! 1046: #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
! 1047: // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
! 1048: #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
! 1049: #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
! 1050: #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
! 1051: #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
! 1052: #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
! 1053: #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
! 1054: #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
! 1055: // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
! 1056: #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
! 1057: #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
! 1058: #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
! 1059: // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
! 1060: #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
! 1061: #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
! 1062: #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
! 1063: #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
! 1064: #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
! 1065: #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
! 1066: // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
! 1067: // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
! 1068: // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
! 1069:
! 1070: // *****************************************************************************
! 1071: // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
! 1072: // *****************************************************************************
! 1073: typedef struct _AT91S_TC {
! 1074: AT91_REG TC_CCR; // Channel Control Register
! 1075: AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
! 1076: AT91_REG Reserved0[2]; //
! 1077: AT91_REG TC_CV; // Counter Value
! 1078: AT91_REG TC_RA; // Register A
! 1079: AT91_REG TC_RB; // Register B
! 1080: AT91_REG TC_RC; // Register C
! 1081: AT91_REG TC_SR; // Status Register
! 1082: AT91_REG TC_IER; // Interrupt Enable Register
! 1083: AT91_REG TC_IDR; // Interrupt Disable Register
! 1084: AT91_REG TC_IMR; // Interrupt Mask Register
! 1085: } AT91S_TC, *AT91PS_TC;
! 1086:
! 1087: // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
! 1088: #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
! 1089: #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
! 1090: #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
! 1091: // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
! 1092: #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
! 1093: #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
! 1094: #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
! 1095: #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
! 1096: #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
! 1097: #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
! 1098: #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
! 1099: #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
! 1100: #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
! 1101: #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
! 1102: #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
! 1103: #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
! 1104: #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
! 1105: #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
! 1106: #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
! 1107: #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
! 1108: #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
! 1109: #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
! 1110: #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
! 1111: #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
! 1112: #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
! 1113: #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
! 1114: #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
! 1115: #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
! 1116: #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
! 1117: #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
! 1118: #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
! 1119: #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
! 1120: #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
! 1121: #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
! 1122: #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
! 1123: #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
! 1124: #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
! 1125: #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
! 1126: #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
! 1127: #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
! 1128: #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
! 1129: #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
! 1130: #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
! 1131: #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
! 1132: #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
! 1133: #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
! 1134: #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
! 1135: #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
! 1136: #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
! 1137: #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
! 1138: #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
! 1139: #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
! 1140: #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
! 1141: #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
! 1142: #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
! 1143: #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
! 1144: #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
! 1145: #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
! 1146: #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
! 1147: #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
! 1148: #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
! 1149: #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
! 1150: #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
! 1151: #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
! 1152: #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
! 1153: #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
! 1154: #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
! 1155: #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
! 1156: #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
! 1157: #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
! 1158: #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
! 1159: #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
! 1160: #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
! 1161: #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
! 1162: #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
! 1163: #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
! 1164: #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
! 1165: #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
! 1166: #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
! 1167: #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
! 1168: #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
! 1169: #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
! 1170: #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
! 1171: #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
! 1172: #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
! 1173: #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
! 1174: #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
! 1175: #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
! 1176: #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
! 1177: #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
! 1178: #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
! 1179: #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
! 1180: #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
! 1181: #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
! 1182: #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
! 1183: #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
! 1184: #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
! 1185: // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
! 1186: #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
! 1187: #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
! 1188: #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
! 1189: #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
! 1190: #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
! 1191: #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
! 1192: #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
! 1193: #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
! 1194: #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
! 1195: #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
! 1196: #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
! 1197: // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
! 1198: // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
! 1199: // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
! 1200:
! 1201: // *****************************************************************************
! 1202: // SOFTWARE API DEFINITION FOR Timer Counter Interface
! 1203: // *****************************************************************************
! 1204: typedef struct _AT91S_TCB {
! 1205: AT91S_TC TCB_TC0; // TC Channel 0
! 1206: AT91_REG Reserved0[4]; //
! 1207: AT91S_TC TCB_TC1; // TC Channel 1
! 1208: AT91_REG Reserved1[4]; //
! 1209: AT91S_TC TCB_TC2; // TC Channel 2
! 1210: AT91_REG Reserved2[4]; //
! 1211: AT91_REG TCB_BCR; // TC Block Control Register
! 1212: AT91_REG TCB_BMR; // TC Block Mode Register
! 1213: } AT91S_TCB, *AT91PS_TCB;
! 1214:
! 1215: // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
! 1216: #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
! 1217: // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
! 1218: #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
! 1219: #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
! 1220: #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
! 1221: #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
! 1222: #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
! 1223: #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
! 1224: #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
! 1225: #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
! 1226: #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
! 1227: #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
! 1228: #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
! 1229: #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
! 1230: #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
! 1231: #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
! 1232: #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
! 1233:
! 1234: // *****************************************************************************
! 1235: // SOFTWARE API DEFINITION FOR PWMC Channel Interface
! 1236: // *****************************************************************************
! 1237: typedef struct _AT91S_PWMC_CH {
! 1238: AT91_REG PWMC_CMR; // Channel Mode Register
! 1239: AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
! 1240: AT91_REG PWMC_CPRDR; // Channel Period Register
! 1241: AT91_REG PWMC_CCNTR; // Channel Counter Register
! 1242: AT91_REG PWMC_CUPDR; // Channel Update Register
! 1243: AT91_REG PWMC_Reserved[3]; // Reserved
! 1244: } AT91S_PWMC_CH, *AT91PS_PWMC_CH;
! 1245:
! 1246: // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
! 1247: #define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
! 1248: #define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
! 1249: #define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
! 1250: #define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
! 1251: #define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
! 1252: #define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
! 1253: #define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
! 1254: // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
! 1255: #define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
! 1256: // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
! 1257: #define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
! 1258: // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
! 1259: #define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
! 1260: // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
! 1261: #define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
! 1262:
! 1263: // *****************************************************************************
! 1264: // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
! 1265: // *****************************************************************************
! 1266: typedef struct _AT91S_PWMC {
! 1267: AT91_REG PWMC_MR; // PWMC Mode Register
! 1268: AT91_REG PWMC_ENA; // PWMC Enable Register
! 1269: AT91_REG PWMC_DIS; // PWMC Disable Register
! 1270: AT91_REG PWMC_SR; // PWMC Status Register
! 1271: AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
! 1272: AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
! 1273: AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
! 1274: AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
! 1275: AT91_REG Reserved0[55]; //
! 1276: AT91_REG PWMC_VR; // PWMC Version Register
! 1277: AT91_REG Reserved1[64]; //
! 1278: AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
! 1279: } AT91S_PWMC, *AT91PS_PWMC;
! 1280:
! 1281: // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
! 1282: #define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
! 1283: #define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
! 1284: #define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
! 1285: #define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
! 1286: #define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
! 1287: #define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
! 1288: // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
! 1289: #define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
! 1290: #define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
! 1291: #define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
! 1292: #define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
! 1293: // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
! 1294: // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
! 1295: // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
! 1296: // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
! 1297: // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
! 1298: // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
! 1299:
! 1300: // *****************************************************************************
! 1301: // SOFTWARE API DEFINITION FOR USB Device Interface
! 1302: // *****************************************************************************
! 1303: typedef struct _AT91S_UDP {
! 1304: AT91_REG UDP_NUM; // Frame Number Register
! 1305: AT91_REG UDP_GLBSTATE; // Global State Register
! 1306: AT91_REG UDP_FADDR; // Function Address Register
! 1307: AT91_REG Reserved0[1]; //
! 1308: AT91_REG UDP_IER; // Interrupt Enable Register
! 1309: AT91_REG UDP_IDR; // Interrupt Disable Register
! 1310: AT91_REG UDP_IMR; // Interrupt Mask Register
! 1311: AT91_REG UDP_ISR; // Interrupt Status Register
! 1312: AT91_REG UDP_ICR; // Interrupt Clear Register
! 1313: AT91_REG Reserved1[1]; //
! 1314: AT91_REG UDP_RSTEP; // Reset Endpoint Register
! 1315: AT91_REG Reserved2[1]; //
! 1316: AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register
! 1317: AT91_REG Reserved3[4]; //
! 1318: AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register
! 1319: AT91_REG Reserved4[5]; //
! 1320: AT91_REG UDP_TXVC; // Transceiver Control Register
! 1321: } AT91S_UDP, *AT91PS_UDP;
! 1322:
! 1323: // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
! 1324: #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
! 1325: #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
! 1326: #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
! 1327: // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
! 1328: #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
! 1329: #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
! 1330: #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
! 1331: #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
! 1332: #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
! 1333: // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
! 1334: #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
! 1335: #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
! 1336: // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
! 1337: #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
! 1338: #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
! 1339: #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
! 1340: #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
! 1341: #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
! 1342: #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
! 1343: #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
! 1344: #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
! 1345: #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
! 1346: // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
! 1347: // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
! 1348: // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
! 1349: #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
! 1350: // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
! 1351: // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
! 1352: #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
! 1353: #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
! 1354: #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
! 1355: #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
! 1356: // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
! 1357: #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
! 1358: #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
! 1359: #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
! 1360: #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
! 1361: #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
! 1362: #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
! 1363: #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
! 1364: #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
! 1365: #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
! 1366: #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
! 1367: #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
! 1368: #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
! 1369: #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
! 1370: #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
! 1371: #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
! 1372: #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
! 1373: #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
! 1374: #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
! 1375: #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
! 1376: // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
! 1377: #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
! 1378:
! 1379: // *****************************************************************************
! 1380: // REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
! 1381: // *****************************************************************************
! 1382: // ========== Register definition for SYS peripheral ==========
! 1383: // ========== Register definition for AIC peripheral ==========
! 1384: #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
! 1385: #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
! 1386: #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
! 1387: #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
! 1388: #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
! 1389: #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
! 1390: #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
! 1391: #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
! 1392: #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
! 1393: #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
! 1394: #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
! 1395: #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
! 1396: #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
! 1397: #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
! 1398: #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
! 1399: #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
! 1400: #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
! 1401: #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
! 1402: // ========== Register definition for PDC_DBGU peripheral ==========
! 1403: #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
! 1404: #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
! 1405: #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
! 1406: #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
! 1407: #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
! 1408: #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
! 1409: #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
! 1410: #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
! 1411: #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
! 1412: #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
! 1413: // ========== Register definition for DBGU peripheral ==========
! 1414: #define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
! 1415: #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
! 1416: #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
! 1417: #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
! 1418: #define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
! 1419: #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
! 1420: #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
! 1421: #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
! 1422: #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
! 1423: #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
! 1424: #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
! 1425: #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
! 1426: // ========== Register definition for PIOA peripheral ==========
! 1427: #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
! 1428: #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
! 1429: #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
! 1430: #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
! 1431: #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
! 1432: #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
! 1433: #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
! 1434: #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
! 1435: #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
! 1436: #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
! 1437: #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
! 1438: #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
! 1439: #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
! 1440: #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
! 1441: #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
! 1442: #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
! 1443: #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
! 1444: #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
! 1445: #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
! 1446: #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
! 1447: #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
! 1448: #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
! 1449: #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
! 1450: #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
! 1451: #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
! 1452: #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
! 1453: #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
! 1454: #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
! 1455: #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
! 1456: // ========== Register definition for CKGR peripheral ==========
! 1457: #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
! 1458: #define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
! 1459: #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
! 1460: // ========== Register definition for PMC peripheral ==========
! 1461: #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
! 1462: #define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
! 1463: #define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
! 1464: #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
! 1465: #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
! 1466: #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
! 1467: #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
! 1468: #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
! 1469: #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
! 1470: #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
! 1471: #define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
! 1472: #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
! 1473: #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
! 1474: #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
! 1475: #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
! 1476: // ========== Register definition for RSTC peripheral ==========
! 1477: #define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
! 1478: #define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
! 1479: #define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
! 1480: // ========== Register definition for RTTC peripheral ==========
! 1481: #define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
! 1482: #define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
! 1483: #define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
! 1484: #define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
! 1485: // ========== Register definition for PITC peripheral ==========
! 1486: #define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
! 1487: #define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
! 1488: #define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
! 1489: #define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
! 1490: // ========== Register definition for WDTC peripheral ==========
! 1491: #define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
! 1492: #define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
! 1493: #define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
! 1494: // ========== Register definition for VREG peripheral ==========
! 1495: #define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
! 1496: // ========== Register definition for MC peripheral ==========
! 1497: #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
! 1498: #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
! 1499: #define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
! 1500: #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
! 1501: #define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
! 1502: #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
! 1503: // ========== Register definition for PDC_SPI peripheral ==========
! 1504: #define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
! 1505: #define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
! 1506: #define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
! 1507: #define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
! 1508: #define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
! 1509: #define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
! 1510: #define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
! 1511: #define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
! 1512: #define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
! 1513: #define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
! 1514: // ========== Register definition for SPI peripheral ==========
! 1515: #define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
! 1516: #define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
! 1517: #define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
! 1518: #define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
! 1519: #define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
! 1520: #define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
! 1521: #define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
! 1522: #define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
! 1523: #define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
! 1524: // ========== Register definition for PDC_ADC peripheral ==========
! 1525: #define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
! 1526: #define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
! 1527: #define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
! 1528: #define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
! 1529: #define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
! 1530: #define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
! 1531: #define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
! 1532: #define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
! 1533: #define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
! 1534: #define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
! 1535: // ========== Register definition for ADC peripheral ==========
! 1536: #define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
! 1537: #define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
! 1538: #define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
! 1539: #define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
! 1540: #define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
! 1541: #define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
! 1542: #define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
! 1543: #define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
! 1544: #define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
! 1545: #define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
! 1546: #define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
! 1547: #define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
! 1548: #define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
! 1549: #define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
! 1550: #define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
! 1551: #define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
! 1552: #define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
! 1553: #define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
! 1554: // ========== Register definition for PDC_SSC peripheral ==========
! 1555: #define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
! 1556: #define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
! 1557: #define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
! 1558: #define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
! 1559: #define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
! 1560: #define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
! 1561: #define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
! 1562: #define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
! 1563: #define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
! 1564: #define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
! 1565: // ========== Register definition for SSC peripheral ==========
! 1566: #define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
! 1567: #define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
! 1568: #define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
! 1569: #define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
! 1570: #define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
! 1571: #define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
! 1572: #define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
! 1573: #define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
! 1574: #define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
! 1575: #define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
! 1576: #define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
! 1577: #define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
! 1578: #define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
! 1579: #define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
! 1580: // ========== Register definition for PDC_US1 peripheral ==========
! 1581: #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
! 1582: #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
! 1583: #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
! 1584: #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
! 1585: #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
! 1586: #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
! 1587: #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
! 1588: #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
! 1589: #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
! 1590: #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
! 1591: // ========== Register definition for US1 peripheral ==========
! 1592: #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
! 1593: #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
! 1594: #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
! 1595: #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
! 1596: #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
! 1597: #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
! 1598: #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
! 1599: #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
! 1600: #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
! 1601: #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
! 1602: #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
! 1603: #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
! 1604: #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
! 1605: #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
! 1606: // ========== Register definition for PDC_US0 peripheral ==========
! 1607: #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
! 1608: #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
! 1609: #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
! 1610: #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
! 1611: #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
! 1612: #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
! 1613: #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
! 1614: #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
! 1615: #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
! 1616: #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
! 1617: // ========== Register definition for US0 peripheral ==========
! 1618: #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
! 1619: #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
! 1620: #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
! 1621: #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
! 1622: #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
! 1623: #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
! 1624: #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
! 1625: #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
! 1626: #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
! 1627: #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
! 1628: #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
! 1629: #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
! 1630: #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
! 1631: #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
! 1632: // ========== Register definition for TWI peripheral ==========
! 1633: #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
! 1634: #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
! 1635: #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
! 1636: #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
! 1637: #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
! 1638: #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
! 1639: #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
! 1640: #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
! 1641: #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
! 1642: #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
! 1643: // ========== Register definition for TC0 peripheral ==========
! 1644: #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
! 1645: #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
! 1646: #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
! 1647: #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
! 1648: #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
! 1649: #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
! 1650: #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
! 1651: #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
! 1652: #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
! 1653: #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
! 1654: // ========== Register definition for TC1 peripheral ==========
! 1655: #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
! 1656: #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
! 1657: #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
! 1658: #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
! 1659: #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
! 1660: #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
! 1661: #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
! 1662: #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
! 1663: #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
! 1664: #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
! 1665: // ========== Register definition for TC2 peripheral ==========
! 1666: #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
! 1667: #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
! 1668: #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
! 1669: #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
! 1670: #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
! 1671: #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
! 1672: #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
! 1673: #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
! 1674: #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
! 1675: #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
! 1676: // ========== Register definition for TCB peripheral ==========
! 1677: #define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
! 1678: #define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
! 1679: // ========== Register definition for PWMC_CH3 peripheral ==========
! 1680: #define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
! 1681: #define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
! 1682: #define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
! 1683: #define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
! 1684: #define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
! 1685: #define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
! 1686: // ========== Register definition for PWMC_CH2 peripheral ==========
! 1687: #define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
! 1688: #define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
! 1689: #define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
! 1690: #define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
! 1691: #define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
! 1692: #define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
! 1693: // ========== Register definition for PWMC_CH1 peripheral ==========
! 1694: #define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
! 1695: #define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
! 1696: #define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
! 1697: #define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
! 1698: #define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
! 1699: #define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
! 1700: // ========== Register definition for PWMC_CH0 peripheral ==========
! 1701: #define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
! 1702: #define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
! 1703: #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
! 1704: #define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
! 1705: #define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
! 1706: #define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
! 1707: // ========== Register definition for PWMC peripheral ==========
! 1708: #define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
! 1709: #define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
! 1710: #define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
! 1711: #define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
! 1712: #define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
! 1713: #define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
! 1714: #define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
! 1715: #define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
! 1716: #define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
! 1717: // ========== Register definition for UDP peripheral ==========
! 1718: #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
! 1719: #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
! 1720: #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
! 1721: #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
! 1722: #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
! 1723: #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
! 1724: #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
! 1725: #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
! 1726: #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
! 1727: #define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
! 1728: #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
! 1729: #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
! 1730:
! 1731: // *****************************************************************************
! 1732: // PIO DEFINITIONS FOR AT91SAM7S64
! 1733: // *****************************************************************************
! 1734: #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
! 1735: #define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0
! 1736: #define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
! 1737: #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
! 1738: #define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1
! 1739: #define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
! 1740: #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
! 1741: #define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data
! 1742: #define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
! 1743: #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
! 1744: #define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
! 1745: #define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0
! 1746: #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
! 1747: #define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave
! 1748: #define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1
! 1749: #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
! 1750: #define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave
! 1751: #define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2
! 1752: #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
! 1753: #define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock
! 1754: #define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3
! 1755: #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
! 1756: #define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync
! 1757: #define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
! 1758: #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
! 1759: #define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock
! 1760: #define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
! 1761: #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
! 1762: #define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data
! 1763: #define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1
! 1764: #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
! 1765: #define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data
! 1766: #define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2
! 1767: #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
! 1768: #define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock
! 1769: #define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input
! 1770: #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
! 1771: #define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2
! 1772: #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
! 1773: #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
! 1774: #define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync
! 1775: #define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0
! 1776: #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
! 1777: #define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data
! 1778: #define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1
! 1779: #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
! 1780: #define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data
! 1781: #define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
! 1782: #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
! 1783: #define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock
! 1784: #define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0
! 1785: #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
! 1786: #define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send
! 1787: #define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1
! 1788: #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
! 1789: #define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send
! 1790: #define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2
! 1791: #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
! 1792: #define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect
! 1793: #define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
! 1794: #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
! 1795: #define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready
! 1796: #define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
! 1797: #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
! 1798: #define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready
! 1799: #define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input
! 1800: #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
! 1801: #define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator
! 1802: #define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input
! 1803: #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
! 1804: #define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data
! 1805: #define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
! 1806: #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
! 1807: #define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1
! 1808: #define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
! 1809: #define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31
! 1810: #define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
! 1811: #define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2
! 1812: #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
! 1813: #define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock
! 1814: #define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input
! 1815: #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
! 1816: #define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data
! 1817: #define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
! 1818: #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
! 1819: #define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data
! 1820: #define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0
! 1821: #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
! 1822: #define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send
! 1823: #define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3
! 1824: #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
! 1825: #define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send
! 1826: #define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger
! 1827: #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
! 1828: #define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data
! 1829: #define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
! 1830:
! 1831: // *****************************************************************************
! 1832: // PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
! 1833: // *****************************************************************************
! 1834: #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
! 1835: #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
! 1836: #define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller
! 1837: #define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved
! 1838: #define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter
! 1839: #define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface
! 1840: #define AT91C_ID_US0 ((unsigned int) 6) // USART 0
! 1841: #define AT91C_ID_US1 ((unsigned int) 7) // USART 1
! 1842: #define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
! 1843: #define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
! 1844: #define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
! 1845: #define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
! 1846: #define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
! 1847: #define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
! 1848: #define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
! 1849: #define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
! 1850: #define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
! 1851: #define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
! 1852: #define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
! 1853: #define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
! 1854: #define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
! 1855: #define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
! 1856: #define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
! 1857: #define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
! 1858: #define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
! 1859: #define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
! 1860: #define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
! 1861: #define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
! 1862: #define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
! 1863: #define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
! 1864: #define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
! 1865: #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
! 1866: #define AT91C_ALL_INT ((unsigned int) 0xC0007FF7) // ALL VALID INTERRUPTS
! 1867:
! 1868: // *****************************************************************************
! 1869: // BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
! 1870: // *****************************************************************************
! 1871: #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
! 1872: #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
! 1873: #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
! 1874: #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
! 1875: #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
! 1876: #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
! 1877: #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
! 1878: #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
! 1879: #define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
! 1880: #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
! 1881: #define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
! 1882: #define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
! 1883: #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
! 1884: #define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
! 1885: #define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
! 1886: #define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
! 1887: #define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
! 1888: #define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
! 1889: #define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
! 1890: #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
! 1891: #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
! 1892: #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
! 1893: #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
! 1894: #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
! 1895: #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
! 1896: #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
! 1897: #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
! 1898: #define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
! 1899: #define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
! 1900: #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
! 1901: #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
! 1902: #define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
! 1903: #define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
! 1904: #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
! 1905:
! 1906: // *****************************************************************************
! 1907: // MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
! 1908: // *****************************************************************************
! 1909: // ISRAM
! 1910: #define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
! 1911: #define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbytes)
! 1912: // IFLASH
! 1913: #define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address
! 1914: #define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal FLASH size in byte (64 Kbytes)
! 1915: #define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 128) // Internal FLASH Page Size: 128 bytes
! 1916: #define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 4096) // Internal FLASH Lock Region Size: 4 Kbytes
! 1917: #define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 256) // Internal FLASH Number of Pages: 256 bytes
! 1918: #define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 8) // Internal FLASH Number of Lock Bits: 8 bytes
! 1919:
! 1920: #endif
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