File: [local] / funnyos / arch / sam7s64 / config.c (download)
Revision 1.5, Tue Nov 13 22:40:33 2007 UTC (16 years, 7 months ago) by nbrk
Branch: MAIN
Changes since 1.4: +49 -8 lines
complete config_machineinit() with "seems ok" early initialization code:
- disable watchdog
- configure main oscillator and PLL through PMC
- enable USART0 (presume in programmed I/O mode for now)
this all is untested (and even stupid), first thing to do is to check
if we really will run at 96 MHz after PMC reprogramming...
|
/*
* $Id: config.c,v 1.5 2007/11/13 22:40:33 nbrk Exp $
*/
#include <sys/types.h>
#include <sys/device.h>
/* devices' regs that we will touch in config_machineinit() */
#include <arch/sam7s64/dev/sapmcreg.h>
#include <arch/sam7s64/dev/sawdtreg.h>
#include <arch/sam7s64/dev/sapioreg.h>
#include <arch/sam7s64/dev/sausartreg.h>
/*
* Configuration file for platform (AT91SAM7S64).
*/
/* device drivers */
extern struct driver root_dr;
extern struct driver cpu_dr;
extern struct driver saapbus_dr;
extern void(*putchar)(char);
void sauart_early_putc(char ch);
/* amount of physical memory, in Bytes */
uint32_t physmem = 16384 /* 16KB :) */;
/*
* Where to attach each device.
*/
struct attachinfo config_attachinfo[] = {
/* child, parent, pminor, loc, intrno, flags */
{ "cpu" , "root", 0, 0, 0, 0 },
{ "saapbus","root", 0, 0, 0, 0 },
{ NULL, NULL, 0, 0, 0, 0 }
};
/*
* Link device names with their drivers.
*/
struct driverinfo config_driverinfo[] = {
/* name, driverp, ninstances (should be -1) */
{ "root", &root_dr, -1 },
{ "cpu" , &cpu_dr, -1 },
{ "saapbus" , &saapbus_dr, -1 },
{ NULL, NULL, 0 }
};
/*
* Machine early-stage initialization hooks.
*/
void
config_machineinit(void)
{
/*
* Initialize critical devices at startup.
*/
/* XXX kill all magic here */
/* disable watchdog */
*(uint32_t)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000 /* WDDIS */;
/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */
(uint32_t)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;
/* wait main osc. to stabilize.. */
while (! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001 )
;
/* set PLL */
*(uint32_t)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;
/* wait.. */
while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)
;
while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)
;
/* select Master Clock and Processor Clock; select (PLL clock / 2) */
*(uint32_t)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;
/* wait.. */
while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)
;
/*
* Initialize USART0.
*/
/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */
*(uint32_t)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030 /* PIN5 | PIN6 */
/* select this pins in Peripheral A */
*(uint32_t)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030 /* now, RXD0 | TXD0 */
/* enable clock to USART0 */
*(uint32_t)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006 /* 6 is ID of USART0 */
/* set baud rate */
*(uint32_t)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313 /* XXX (48000000 / 9600 * 16) */
/* select usart mode */
*(uint32_t)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0 /* XXX eleminate magic */
/* TODO enable DMA transfers for TX/RX in PDC */
/* enable transmitter/receiver */
*(uint32_t)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050 /* TXEN | RXEN */
/* TODO redefine putchar */
//putchar = sausart_0_putchar;
}