Annotation of funnyos/arch/sam7s64/config.c, Revision 1.8
1.1 init 1: /*
1.8 ! nbrk 2: * $Id: config.c,v 1.7 2007/11/15 20:50:48 nbrk Exp $
1.1 init 3: */
4: #include <sys/types.h>
5: #include <sys/device.h>
6:
1.4 nbrk 7: /* devices' regs that we will touch in config_machineinit() */
8: #include <arch/sam7s64/dev/sapmcreg.h>
1.5 nbrk 9: #include <arch/sam7s64/dev/sawdtreg.h>
10: #include <arch/sam7s64/dev/sapioreg.h>
11: #include <arch/sam7s64/dev/sausartreg.h>
1.4 nbrk 12:
1.1 init 13: /*
14: * Configuration file for platform (AT91SAM7S64).
15: */
16:
17: /* device drivers */
18: extern struct driver root_dr;
19: extern struct driver cpu_dr;
1.3 init 20: extern struct driver saapbus_dr;
1.7 nbrk 21: extern struct driver sapio_dr;
1.8 ! nbrk 22: extern struct driver gpioled_dr;
1.1 init 23:
24:
25: extern void(*putchar)(char);
1.2 init 26: void sauart_early_putc(char ch);
1.1 init 27:
28: /* amount of physical memory, in Bytes */
1.5 nbrk 29: uint32_t physmem = 16384 /* 16KB :) */;
1.1 init 30:
31: /*
32: * Where to attach each device.
33: */
34: struct attachinfo config_attachinfo[] = {
35: /* child, parent, pminor, loc, intrno, flags */
36: { "cpu" , "root", 0, 0, 0, 0 },
1.3 init 37: { "saapbus","root", 0, 0, 0, 0 },
1.7 nbrk 38: { "sapio", "saapbus", 0, 0, 0, 0 },
1.8 ! nbrk 39: { "gpioled","sapio", 0, 17, 0, 0 },
! 40: { "gpioled","sapio", 0, 18, 0, 0 },
1.1 init 41: { NULL, NULL, 0, 0, 0, 0 }
42: };
43:
44:
45: /*
46: * Link device names with their drivers.
47: */
48: struct driverinfo config_driverinfo[] = {
49: /* name, driverp, ninstances (should be -1) */
50: { "root", &root_dr, -1 },
51: { "cpu" , &cpu_dr, -1 },
1.3 init 52: { "saapbus" , &saapbus_dr, -1 },
1.7 nbrk 53: { "sapio", &sapio_dr, -1 },
1.8 ! nbrk 54: { "gpioled", &gpioled_dr, -1 },
1.1 init 55: { NULL, NULL, 0 }
56: };
57:
58:
59: /*
60: * Machine early-stage initialization hooks.
61: */
62:
63: void
1.4 nbrk 64: config_machineinit(void)
1.1 init 65: {
66: /*
1.4 nbrk 67: * Initialize critical devices at startup.
1.1 init 68: */
1.4 nbrk 69:
1.5 nbrk 70: /* XXX kill all magic here */
1.4 nbrk 71:
1.5 nbrk 72: /* disable watchdog */
1.6 nbrk 73: *(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */;
1.4 nbrk 74:
1.5 nbrk 75: /* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */
1.6 nbrk 76: *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;
1.4 nbrk 77: /* wait main osc. to stabilize.. */
1.6 nbrk 78: while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001)
1.4 nbrk 79: ;
80:
1.5 nbrk 81: /* set PLL */
1.6 nbrk 82: *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;
1.5 nbrk 83: /* wait.. */
1.6 nbrk 84: while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)
1.5 nbrk 85: ;
1.6 nbrk 86: while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)
1.5 nbrk 87: ;
88:
89: /* select Master Clock and Processor Clock; select (PLL clock / 2) */
1.6 nbrk 90: *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;
1.5 nbrk 91: /* wait.. */
1.6 nbrk 92: while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)
1.5 nbrk 93: ;
94:
95: /*
1.6 nbrk 96: * Enable clock to PIO.
97: */
98: *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */
99:
100: /*
1.5 nbrk 101: * Initialize USART0.
102: */
103: /* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */
1.6 nbrk 104: *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */
1.5 nbrk 105: /* select this pins in Peripheral A */
1.6 nbrk 106: *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */
1.5 nbrk 107:
108: /* enable clock to USART0 */
1.6 nbrk 109: *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */
1.5 nbrk 110:
111: /* set baud rate */
1.6 nbrk 112: *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */
1.5 nbrk 113:
114: /* select usart mode */
1.6 nbrk 115: *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */
1.5 nbrk 116:
117: /* TODO enable DMA transfers for TX/RX in PDC */
118:
119: /* enable transmitter/receiver */
1.6 nbrk 120: *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */
1.5 nbrk 121:
122: /* TODO redefine putchar */
123: //putchar = sausart_0_putchar;
1.1 init 124: }
125:
126:
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