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Annotation of funnyos/arch/sam7s64/config.c, Revision 1.18

1.1       init        1: /*
1.18    ! nbrk        2:  * $Id: config.c,v 1.17 2007/12/25 14:11:18 nbrk Exp $
1.1       init        3:  */
                      4: #include <sys/types.h>
                      5: #include <sys/device.h>
                      6:
1.9       nbrk        7: #include <dev/cpuvar.h>
                      8: #include <arch/sam7s64/dev/at91sam7.h>
1.4       nbrk        9:
1.1       init       10: /*
                     11:  * Configuration file for platform (AT91SAM7S64).
                     12:  */
                     13:
                     14: /* device drivers */
                     15: extern struct driver root_dr;
                     16: extern struct driver cpu_dr;
1.3       init       17: extern struct driver saapbus_dr;
1.7       nbrk       18: extern struct driver sapio_dr;
1.8       nbrk       19: extern struct driver gpioled_dr;
1.13      nbrk       20: extern struct driver saaic_dr;
                     21: extern struct driver sartt_dr;
1.14      nbrk       22: extern struct driver gpiobtn_dr;
1.15      nbrk       23: extern struct driver saspi_dr;
1.16      nbrk       24: extern struct driver spisdmmc_dr;
1.17      nbrk       25: extern struct driver sdmmc_dr;
1.18    ! nbrk       26: extern struct driver gpio7seg_dr;
1.1       init       27:
1.9       nbrk       28: extern void    (*putchar)(char);
1.10      nbrk       29: extern void    sausart_early_putchar(char ch);
1.1       init       30:
                     31: /* amount of physical memory, in Bytes */
1.5       nbrk       32: uint32_t physmem = 16384 /* 16KB :) */;
1.1       init       33:
                     34: /*
                     35:  * Where to attach each device.
                     36:  */
                     37: struct attachinfo config_attachinfo[] = {
                     38:        /* child,   parent, pminor, loc,        intrno, flags */
1.14      nbrk       39:        { "cpu" ,       "root",         0, 0,                   -1,     0 },
                     40:        { "saapbus","root",     0, 0,                   -1,     0 },
                     41:        { "sapio",  "saapbus",  0, 0,                   -1, 0 },
                     42:        { "gpioled","sapio",    0, 17,                  -1, 0 },
                     43:        { "gpioled","sapio",    0, 18,                  -1, 0 },
                     44:        { "gpiobtn","sapio",    0, 19,                   0,     0 /*controls gpioled/0*/},
                     45:        { "gpiobtn","sapio",    0, 20,                  30,     0 /*controls gpioled/1*/},
1.18    ! nbrk       46:        { "gpio7seg","sapio",   0, 0,                   -1, 0 },
1.14      nbrk       47: //     { "sartt",  "saapbus",  0, 0,                   1,  0 },
1.15      nbrk       48:        { "saspi",      "saapbus",      0, 0,                   0,      0 },
1.18    ! nbrk       49: //     { "spisdmmc","saspi",   0, 0,                   0,      0 },
        !            50: //     { "sdmmc",      "spisdmmc", 0, 0,                       0,      0 },
1.15      nbrk       51: //     { "saaic",  "saapbus",  0, 0,                   -1, 0 },
1.14      nbrk       52:        { NULL,         NULL,           0, 0,                   -1,  0 }
1.1       init       53: };
                     54:
                     55:
                     56: /*
                     57:  * Link device names with their drivers.
                     58:  */
                     59: struct driverinfo config_driverinfo[] = {
                     60: /* name, driverp, ninstances (should be -1) */
                     61:        { "root", &root_dr, -1 },
                     62:        { "cpu" , &cpu_dr, -1 },
1.3       init       63:        { "saapbus" , &saapbus_dr, -1 },
1.7       nbrk       64:        { "sapio", &sapio_dr, -1 },
1.8       nbrk       65:        { "gpioled", &gpioled_dr, -1 },
1.13      nbrk       66:        { "saaic", &saaic_dr, -1 },
                     67:        { "sartt", &sartt_dr, -1 },
1.15      nbrk       68:        { "gpiobtn", &gpiobtn_dr, -1 },
                     69:        { "saspi", &saspi_dr, -1 },
1.16      nbrk       70:        { "spisdmmc", &spisdmmc_dr, -1 },
1.17      nbrk       71:        { "sdmmc", &sdmmc_dr, -1 },
1.18    ! nbrk       72:        { "gpio7seg", &gpio7seg_dr, -1 },
1.1       init       73:        { NULL, NULL, 0 }
                     74: };
                     75:
                     76:
                     77: /*
                     78:  * Machine early-stage initialization hooks.
                     79:  */
                     80:
                     81: void
1.4       nbrk       82: config_machineinit(void)
1.1       init       83: {
                     84:        /*
1.4       nbrk       85:         * Initialize critical devices at startup.
1.1       init       86:         */
1.9       nbrk       87:        __cpu_disable_irq();
1.4       nbrk       88:
1.5       nbrk       89:        /* disable watchdog */
1.9       nbrk       90:        *AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
1.5       nbrk       91:
1.9       nbrk       92:        /* set FLASH to high-speed */
                     93:        *AT91C_MC_FMR = AT91C_MC_FWS_0FWS;
1.5       nbrk       94:
1.11      nbrk       95:        /* enable user RESET (magic button on board) */
                     96:        *AT91C_RSTC_RMR = AT91C_RSTC_URSTEN | AT91C_RSTC_KEY;
                     97:
1.5       nbrk       98:        /*
1.9       nbrk       99:         * Initialize oscillators.
                    100:         * Taken from Atmel's examples.
1.6       nbrk      101:         */
1.9       nbrk      102:        /* Set MCK at 48 054 850 */
1.6       nbrk      103:
1.9       nbrk      104:        /* 1 Enabling the Main Oscillator */
                    105:     /* SCK = 1/32768 = 30.51 uSecond
                    106:      * Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
1.5       nbrk      107:         */
1.9       nbrk      108:        *AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN);
1.5       nbrk      109:
1.9       nbrk      110:        /* Wait the startup time */
                    111:        while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS))
                    112:                ;
1.5       nbrk      113:
1.9       nbrk      114:        /* 2 Checking the Main Oscillator Frequency (Optional) */
                    115:        /* TODO */
1.5       nbrk      116:
1.9       nbrk      117:        /* 3 Setting PLL and divider: */
                    118:        /* - div by 14 Fin = 1.3165 =(18,432 / 14)
                    119:         * - Mul 72+1: Fout =   96.1097 =(3,6864 *73)
                    120:         * for 96 MHz the erroe is 0.11%
                    121:         * Field out NOT USED = 0
                    122:         * PLLCOUNT pll startup time estimate at : 0.844 ms
                    123:         * PLLCOUNT 28 = 0.000844 /(1/32768)
                    124:         */
                    125:        *AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 )              |
                    126:                                        (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                    127:                                        (AT91C_CKGR_MUL & (72<<16)) );
1.5       nbrk      128:
1.9       nbrk      129:        /* Wait the startup time */
                    130:        while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK))
                    131:                ;
                    132:        while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                    133:                ;
1.5       nbrk      134:
1.9       nbrk      135:        /* 4. Selection of Master Clock and Processor Clock */
                    136:        /* select the PLL clock divided by 2: */
                    137:        *AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2;
                    138:        while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                    139:                ;
                    140:
                    141:        *AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
                    142:        while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                    143:                ;
1.5       nbrk      144:
1.12      nbrk      145:        /* enable clock to all modules */
1.11      nbrk      146:        *AT91C_PMC_PCER = AT91C_ALL_INT;
1.9       nbrk      147:
                    148:        /* initialize USART0 (we clock it in PMC above) */
                    149:
                    150:   *AT91C_PIOA_PDR = AT91C_PA5_RXD0 |        /* Enable RxD0 Pin */
                    151:                     AT91C_PA6_TXD0;         /* Enalbe TxD0 Pin */
                    152:
                    153:   *AT91C_US0_MR = AT91C_US_USMODE_NORMAL |  /* Normal Mode */
                    154:                   AT91C_US_CLKS_CLOCK    |  /* Clock = MCK */
                    155:                   AT91C_US_CHRL_8_BITS   |  /* 8-bit Data  */
                    156:                   AT91C_US_PAR_NONE      |  /* No Parity   */
                    157:                   AT91C_US_NBSTOP_1_BIT;    /* 1 Stop Bit  */
                    158:
                    159:   *AT91C_US0_BRGR = 48054857 / 16 / 9600;                    /* Baud Rate Divisor */
                    160:
1.10      nbrk      161:   /* enable DMA transfers on USART0 */
                    162:   *AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN;
                    163:
1.9       nbrk      164:   *AT91C_US0_CR = AT91C_US_RXEN  |          /* Receiver Enable     */
                    165:                   AT91C_US_TXEN;            /* Transmitter Enable  */
                    166:
                    167:        /* redefine putchar */
1.10      nbrk      168:        putchar = sausart_early_putchar;
1.1       init      169: }
                    170:
                    171:

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