Annotation of funnyos/arch/sam7s64/config.c, Revision 1.15
1.1 init 1: /*
1.15 ! nbrk 2: * $Id: config.c,v 1.14 2007/12/16 23:16:09 nbrk Exp $
1.1 init 3: */
4: #include <sys/types.h>
5: #include <sys/device.h>
6:
1.9 nbrk 7: #include <dev/cpuvar.h>
8: #include <arch/sam7s64/dev/at91sam7.h>
1.4 nbrk 9:
1.1 init 10: /*
11: * Configuration file for platform (AT91SAM7S64).
12: */
13:
14: /* device drivers */
15: extern struct driver root_dr;
16: extern struct driver cpu_dr;
1.3 init 17: extern struct driver saapbus_dr;
1.7 nbrk 18: extern struct driver sapio_dr;
1.8 nbrk 19: extern struct driver gpioled_dr;
1.13 nbrk 20: extern struct driver saaic_dr;
21: extern struct driver sartt_dr;
1.14 nbrk 22: extern struct driver gpiobtn_dr;
1.15 ! nbrk 23: extern struct driver saspi_dr;
1.1 init 24:
25:
1.9 nbrk 26: extern void (*putchar)(char);
1.10 nbrk 27: extern void sausart_early_putchar(char ch);
1.1 init 28:
29: /* amount of physical memory, in Bytes */
1.5 nbrk 30: uint32_t physmem = 16384 /* 16KB :) */;
1.1 init 31:
32: /*
33: * Where to attach each device.
34: */
35: struct attachinfo config_attachinfo[] = {
36: /* child, parent, pminor, loc, intrno, flags */
1.14 nbrk 37: { "cpu" , "root", 0, 0, -1, 0 },
38: { "saapbus","root", 0, 0, -1, 0 },
39: { "sapio", "saapbus", 0, 0, -1, 0 },
40: { "gpioled","sapio", 0, 17, -1, 0 },
41: { "gpioled","sapio", 0, 18, -1, 0 },
42: { "gpiobtn","sapio", 0, 19, 0, 0 /*controls gpioled/0*/},
43: { "gpiobtn","sapio", 0, 20, 30, 0 /*controls gpioled/1*/},
44: // { "sartt", "saapbus", 0, 0, 1, 0 },
1.15 ! nbrk 45: { "saspi", "saapbus", 0, 0, 0, 0 },
! 46: // { "saaic", "saapbus", 0, 0, -1, 0 },
1.14 nbrk 47: { NULL, NULL, 0, 0, -1, 0 }
1.1 init 48: };
49:
50:
51: /*
52: * Link device names with their drivers.
53: */
54: struct driverinfo config_driverinfo[] = {
55: /* name, driverp, ninstances (should be -1) */
56: { "root", &root_dr, -1 },
57: { "cpu" , &cpu_dr, -1 },
1.3 init 58: { "saapbus" , &saapbus_dr, -1 },
1.7 nbrk 59: { "sapio", &sapio_dr, -1 },
1.8 nbrk 60: { "gpioled", &gpioled_dr, -1 },
1.13 nbrk 61: { "saaic", &saaic_dr, -1 },
62: { "sartt", &sartt_dr, -1 },
1.15 ! nbrk 63: { "gpiobtn", &gpiobtn_dr, -1 },
! 64: { "saspi", &saspi_dr, -1 },
1.1 init 65: { NULL, NULL, 0 }
66: };
67:
68:
69: /*
70: * Machine early-stage initialization hooks.
71: */
72:
73: void
1.4 nbrk 74: config_machineinit(void)
1.1 init 75: {
76: /*
1.4 nbrk 77: * Initialize critical devices at startup.
1.1 init 78: */
1.9 nbrk 79: __cpu_disable_irq();
1.4 nbrk 80:
1.5 nbrk 81: /* disable watchdog */
1.9 nbrk 82: *AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
1.5 nbrk 83:
1.9 nbrk 84: /* set FLASH to high-speed */
85: *AT91C_MC_FMR = AT91C_MC_FWS_0FWS;
1.5 nbrk 86:
1.11 nbrk 87: /* enable user RESET (magic button on board) */
88: *AT91C_RSTC_RMR = AT91C_RSTC_URSTEN | AT91C_RSTC_KEY;
89:
1.5 nbrk 90: /*
1.9 nbrk 91: * Initialize oscillators.
92: * Taken from Atmel's examples.
1.6 nbrk 93: */
1.9 nbrk 94: /* Set MCK at 48 054 850 */
1.6 nbrk 95:
1.9 nbrk 96: /* 1 Enabling the Main Oscillator */
97: /* SCK = 1/32768 = 30.51 uSecond
98: * Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
1.5 nbrk 99: */
1.9 nbrk 100: *AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN);
1.5 nbrk 101:
1.9 nbrk 102: /* Wait the startup time */
103: while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS))
104: ;
1.5 nbrk 105:
1.9 nbrk 106: /* 2 Checking the Main Oscillator Frequency (Optional) */
107: /* TODO */
1.5 nbrk 108:
1.9 nbrk 109: /* 3 Setting PLL and divider: */
110: /* - div by 14 Fin = 1.3165 =(18,432 / 14)
111: * - Mul 72+1: Fout = 96.1097 =(3,6864 *73)
112: * for 96 MHz the erroe is 0.11%
113: * Field out NOT USED = 0
114: * PLLCOUNT pll startup time estimate at : 0.844 ms
115: * PLLCOUNT 28 = 0.000844 /(1/32768)
116: */
117: *AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 ) |
118: (AT91C_CKGR_PLLCOUNT & (28<<8)) |
119: (AT91C_CKGR_MUL & (72<<16)) );
1.5 nbrk 120:
1.9 nbrk 121: /* Wait the startup time */
122: while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK))
123: ;
124: while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
125: ;
1.5 nbrk 126:
1.9 nbrk 127: /* 4. Selection of Master Clock and Processor Clock */
128: /* select the PLL clock divided by 2: */
129: *AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2;
130: while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
131: ;
132:
133: *AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
134: while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
135: ;
1.5 nbrk 136:
1.12 nbrk 137: /* enable clock to all modules */
1.11 nbrk 138: *AT91C_PMC_PCER = AT91C_ALL_INT;
1.9 nbrk 139:
140: /* initialize USART0 (we clock it in PMC above) */
141:
142: *AT91C_PIOA_PDR = AT91C_PA5_RXD0 | /* Enable RxD0 Pin */
143: AT91C_PA6_TXD0; /* Enalbe TxD0 Pin */
144:
145: *AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */
146: AT91C_US_CLKS_CLOCK | /* Clock = MCK */
147: AT91C_US_CHRL_8_BITS | /* 8-bit Data */
148: AT91C_US_PAR_NONE | /* No Parity */
149: AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */
150:
151: *AT91C_US0_BRGR = 48054857 / 16 / 9600; /* Baud Rate Divisor */
152:
1.10 nbrk 153: /* enable DMA transfers on USART0 */
154: *AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN;
155:
1.9 nbrk 156: *AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */
157: AT91C_US_TXEN; /* Transmitter Enable */
158:
159: /* redefine putchar */
1.10 nbrk 160: putchar = sausart_early_putchar;
1.1 init 161: }
162:
163:
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