[BACK]Return to config.c CVS log [TXT][DIR] Up to [local] / funnyos / arch / sam7s64

Annotation of funnyos/arch/sam7s64/config.c, Revision 1.13

1.1       init        1: /*
1.13    ! nbrk        2:  * $Id: config.c,v 1.12 2007/11/24 17:45:19 nbrk Exp $
1.1       init        3:  */
                      4: #include <sys/types.h>
                      5: #include <sys/device.h>
                      6:
1.9       nbrk        7: #include <dev/cpuvar.h>
                      8: #include <arch/sam7s64/dev/at91sam7.h>
1.4       nbrk        9:
1.1       init       10: /*
                     11:  * Configuration file for platform (AT91SAM7S64).
                     12:  */
                     13:
                     14: /* device drivers */
                     15: extern struct driver root_dr;
                     16: extern struct driver cpu_dr;
1.3       init       17: extern struct driver saapbus_dr;
1.7       nbrk       18: extern struct driver sapio_dr;
1.8       nbrk       19: extern struct driver gpioled_dr;
1.13    ! nbrk       20: extern struct driver saaic_dr;
        !            21: extern struct driver sartt_dr;
1.1       init       22:
                     23:
1.9       nbrk       24: extern void    (*putchar)(char);
1.10      nbrk       25: extern void    sausart_early_putchar(char ch);
1.1       init       26:
                     27: /* amount of physical memory, in Bytes */
1.5       nbrk       28: uint32_t physmem = 16384 /* 16KB :) */;
1.1       init       29:
                     30: /*
                     31:  * Where to attach each device.
                     32:  */
                     33: struct attachinfo config_attachinfo[] = {
                     34:        /* child,   parent, pminor, loc,        intrno, flags */
                     35:        { "cpu" ,       "root",         0, 0,                   0,      0 },
1.3       init       36:        { "saapbus","root",     0, 0,                   0,      0 },
1.7       nbrk       37:        { "sapio",  "saapbus",  0, 0,                   0,  0 },
1.8       nbrk       38:        { "gpioled","sapio",    0, 17,                  0,      0 },
                     39:        { "gpioled","sapio",    0, 18,                  0,      0 },
1.13    ! nbrk       40:        { "sartt",  "saapbus",  0, 0,                   1,  0 },
        !            41:        { "saaic",  "saapbus",  0, 0,                   0,  0 },
1.1       init       42:        { NULL,         NULL,           0, 0,                   0,  0 }
                     43: };
                     44:
                     45:
                     46: /*
                     47:  * Link device names with their drivers.
                     48:  */
                     49: struct driverinfo config_driverinfo[] = {
                     50: /* name, driverp, ninstances (should be -1) */
                     51:        { "root", &root_dr, -1 },
                     52:        { "cpu" , &cpu_dr, -1 },
1.3       init       53:        { "saapbus" , &saapbus_dr, -1 },
1.7       nbrk       54:        { "sapio", &sapio_dr, -1 },
1.8       nbrk       55:        { "gpioled", &gpioled_dr, -1 },
1.13    ! nbrk       56:        { "saaic", &saaic_dr, -1 },
        !            57:        { "sartt", &sartt_dr, -1 },
1.1       init       58:        { NULL, NULL, 0 }
                     59: };
                     60:
                     61:
                     62: /*
                     63:  * Machine early-stage initialization hooks.
                     64:  */
                     65:
                     66: void
1.4       nbrk       67: config_machineinit(void)
1.1       init       68: {
                     69:        /*
1.4       nbrk       70:         * Initialize critical devices at startup.
1.1       init       71:         */
1.9       nbrk       72:        __cpu_disable_irq();
1.4       nbrk       73:
1.5       nbrk       74:        /* disable watchdog */
1.9       nbrk       75:        *AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
1.5       nbrk       76:
1.9       nbrk       77:        /* set FLASH to high-speed */
                     78:        *AT91C_MC_FMR = AT91C_MC_FWS_0FWS;
1.5       nbrk       79:
1.11      nbrk       80:        /* enable user RESET (magic button on board) */
                     81:        *AT91C_RSTC_RMR = AT91C_RSTC_URSTEN | AT91C_RSTC_KEY;
                     82:
1.5       nbrk       83:        /*
1.9       nbrk       84:         * Initialize oscillators.
                     85:         * Taken from Atmel's examples.
1.6       nbrk       86:         */
1.9       nbrk       87:        /* Set MCK at 48 054 850 */
1.6       nbrk       88:
1.9       nbrk       89:        /* 1 Enabling the Main Oscillator */
                     90:     /* SCK = 1/32768 = 30.51 uSecond
                     91:      * Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
1.5       nbrk       92:         */
1.9       nbrk       93:        *AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN);
1.5       nbrk       94:
1.9       nbrk       95:        /* Wait the startup time */
                     96:        while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS))
                     97:                ;
1.5       nbrk       98:
1.9       nbrk       99:        /* 2 Checking the Main Oscillator Frequency (Optional) */
                    100:        /* TODO */
1.5       nbrk      101:
1.9       nbrk      102:        /* 3 Setting PLL and divider: */
                    103:        /* - div by 14 Fin = 1.3165 =(18,432 / 14)
                    104:         * - Mul 72+1: Fout =   96.1097 =(3,6864 *73)
                    105:         * for 96 MHz the erroe is 0.11%
                    106:         * Field out NOT USED = 0
                    107:         * PLLCOUNT pll startup time estimate at : 0.844 ms
                    108:         * PLLCOUNT 28 = 0.000844 /(1/32768)
                    109:         */
                    110:        *AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 )              |
                    111:                                        (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                    112:                                        (AT91C_CKGR_MUL & (72<<16)) );
1.5       nbrk      113:
1.9       nbrk      114:        /* Wait the startup time */
                    115:        while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK))
                    116:                ;
                    117:        while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                    118:                ;
1.5       nbrk      119:
1.9       nbrk      120:        /* 4. Selection of Master Clock and Processor Clock */
                    121:        /* select the PLL clock divided by 2: */
                    122:        *AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2;
                    123:        while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                    124:                ;
                    125:
                    126:        *AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
                    127:        while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                    128:                ;
1.5       nbrk      129:
1.12      nbrk      130:        /* enable clock to all modules */
1.11      nbrk      131:        *AT91C_PMC_PCER = AT91C_ALL_INT;
1.9       nbrk      132:
                    133:        /* initialize USART0 (we clock it in PMC above) */
                    134:
                    135:   *AT91C_PIOA_PDR = AT91C_PA5_RXD0 |        /* Enable RxD0 Pin */
                    136:                     AT91C_PA6_TXD0;         /* Enalbe TxD0 Pin */
                    137:
                    138:   *AT91C_US0_MR = AT91C_US_USMODE_NORMAL |  /* Normal Mode */
                    139:                   AT91C_US_CLKS_CLOCK    |  /* Clock = MCK */
                    140:                   AT91C_US_CHRL_8_BITS   |  /* 8-bit Data  */
                    141:                   AT91C_US_PAR_NONE      |  /* No Parity   */
                    142:                   AT91C_US_NBSTOP_1_BIT;    /* 1 Stop Bit  */
                    143:
                    144:   *AT91C_US0_BRGR = 48054857 / 16 / 9600;                    /* Baud Rate Divisor */
                    145:
1.10      nbrk      146:   /* enable DMA transfers on USART0 */
                    147:   *AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN;
                    148:
1.9       nbrk      149:   *AT91C_US0_CR = AT91C_US_RXEN  |          /* Receiver Enable     */
                    150:                   AT91C_US_TXEN;            /* Transmitter Enable  */
                    151:
                    152:        /* redefine putchar */
1.10      nbrk      153:        putchar = sausart_early_putchar;
1.1       init      154: }
                    155:
                    156:

CVSweb