Annotation of funnyos/arch/sam7s64/config.c, Revision 1.11
1.1 init 1: /*
1.11 ! nbrk 2: * $Id: config.c,v 1.10 2007/11/24 15:13:33 nbrk Exp $
1.1 init 3: */
4: #include <sys/types.h>
5: #include <sys/device.h>
6:
1.9 nbrk 7: #include <dev/cpuvar.h>
8: #include <arch/sam7s64/dev/at91sam7.h>
1.4 nbrk 9:
1.1 init 10: /*
11: * Configuration file for platform (AT91SAM7S64).
12: */
13:
14: /* device drivers */
15: extern struct driver root_dr;
16: extern struct driver cpu_dr;
1.3 init 17: extern struct driver saapbus_dr;
1.7 nbrk 18: extern struct driver sapio_dr;
1.8 nbrk 19: extern struct driver gpioled_dr;
1.1 init 20:
21:
1.9 nbrk 22: extern void (*putchar)(char);
1.10 nbrk 23: extern void sausart_early_putchar(char ch);
1.1 init 24:
25: /* amount of physical memory, in Bytes */
1.5 nbrk 26: uint32_t physmem = 16384 /* 16KB :) */;
1.1 init 27:
28: /*
29: * Where to attach each device.
30: */
31: struct attachinfo config_attachinfo[] = {
32: /* child, parent, pminor, loc, intrno, flags */
33: { "cpu" , "root", 0, 0, 0, 0 },
1.3 init 34: { "saapbus","root", 0, 0, 0, 0 },
1.7 nbrk 35: { "sapio", "saapbus", 0, 0, 0, 0 },
1.8 nbrk 36: { "gpioled","sapio", 0, 17, 0, 0 },
37: { "gpioled","sapio", 0, 18, 0, 0 },
1.1 init 38: { NULL, NULL, 0, 0, 0, 0 }
39: };
40:
41:
42: /*
43: * Link device names with their drivers.
44: */
45: struct driverinfo config_driverinfo[] = {
46: /* name, driverp, ninstances (should be -1) */
47: { "root", &root_dr, -1 },
48: { "cpu" , &cpu_dr, -1 },
1.3 init 49: { "saapbus" , &saapbus_dr, -1 },
1.7 nbrk 50: { "sapio", &sapio_dr, -1 },
1.8 nbrk 51: { "gpioled", &gpioled_dr, -1 },
1.1 init 52: { NULL, NULL, 0 }
53: };
54:
55:
56: /*
57: * Machine early-stage initialization hooks.
58: */
59:
60: void
1.4 nbrk 61: config_machineinit(void)
1.1 init 62: {
63: /*
1.4 nbrk 64: * Initialize critical devices at startup.
1.1 init 65: */
1.9 nbrk 66: __cpu_disable_irq();
1.4 nbrk 67:
1.5 nbrk 68: /* disable watchdog */
1.9 nbrk 69: *AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
1.5 nbrk 70:
1.9 nbrk 71: /* set FLASH to high-speed */
72: *AT91C_MC_FMR = AT91C_MC_FWS_0FWS;
1.5 nbrk 73:
1.11 ! nbrk 74: /* enable user RESET (magic button on board) */
! 75: *AT91C_RSTC_RMR = AT91C_RSTC_URSTEN | AT91C_RSTC_KEY;
! 76:
1.5 nbrk 77: /*
1.9 nbrk 78: * Initialize oscillators.
79: * Taken from Atmel's examples.
1.6 nbrk 80: */
1.9 nbrk 81: /* Set MCK at 48 054 850 */
1.6 nbrk 82:
1.9 nbrk 83: /* 1 Enabling the Main Oscillator */
84: /* SCK = 1/32768 = 30.51 uSecond
85: * Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
1.5 nbrk 86: */
1.9 nbrk 87: *AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN);
1.5 nbrk 88:
1.9 nbrk 89: /* Wait the startup time */
90: while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS))
91: ;
1.5 nbrk 92:
1.9 nbrk 93: /* 2 Checking the Main Oscillator Frequency (Optional) */
94: /* TODO */
1.5 nbrk 95:
1.9 nbrk 96: /* 3 Setting PLL and divider: */
97: /* - div by 14 Fin = 1.3165 =(18,432 / 14)
98: * - Mul 72+1: Fout = 96.1097 =(3,6864 *73)
99: * for 96 MHz the erroe is 0.11%
100: * Field out NOT USED = 0
101: * PLLCOUNT pll startup time estimate at : 0.844 ms
102: * PLLCOUNT 28 = 0.000844 /(1/32768)
103: */
104: *AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 ) |
105: (AT91C_CKGR_PLLCOUNT & (28<<8)) |
106: (AT91C_CKGR_MUL & (72<<16)) );
1.5 nbrk 107:
1.9 nbrk 108: /* Wait the startup time */
109: while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK))
110: ;
111: while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
112: ;
1.5 nbrk 113:
1.9 nbrk 114: /* 4. Selection of Master Clock and Processor Clock */
115: /* select the PLL clock divided by 2: */
116: *AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2;
117: while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
118: ;
119:
120: *AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
121: while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
122: ;
1.5 nbrk 123:
1.9 nbrk 124: /* enable clock to PIO and USART0 */
1.11 ! nbrk 125: //*AT91C_PMC_PCER = AT91C_ID_PIOA | AT91C_ID_US0;
! 126: *AT91C_PMC_PCER = AT91C_ALL_INT;
1.9 nbrk 127:
128: *AT91C_PIOA_PER = (1 << 17 | 1 << 18);
129: *AT91C_PIOA_OER = (1 << 17 | 1 << 18);
130: *AT91C_PIOA_CODR= (1 << 17 | 1 << 18);
131:
132: /* initialize USART0 (we clock it in PMC above) */
133:
134: *AT91C_PIOA_PDR = AT91C_PA5_RXD0 | /* Enable RxD0 Pin */
135: AT91C_PA6_TXD0; /* Enalbe TxD0 Pin */
136:
137: *AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */
138: AT91C_US_CLKS_CLOCK | /* Clock = MCK */
139: AT91C_US_CHRL_8_BITS | /* 8-bit Data */
140: AT91C_US_PAR_NONE | /* No Parity */
141: AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */
142:
143: *AT91C_US0_BRGR = 48054857 / 16 / 9600; /* Baud Rate Divisor */
144:
1.10 nbrk 145: /* enable DMA transfers on USART0 */
146: *AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN;
147:
1.9 nbrk 148: *AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */
149: AT91C_US_TXEN; /* Transmitter Enable */
150:
151: /* redefine putchar */
1.10 nbrk 152: putchar = sausart_early_putchar;
1.1 init 153: }
154:
155:
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