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Diff for /funnyos/arch/sam7s64/config.c between version 1.8 and 1.9

version 1.8, 2007/11/19 10:53:57 version 1.9, 2007/11/24 10:12:44
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 #include <sys/types.h>  #include <sys/types.h>
 #include <sys/device.h>  #include <sys/device.h>
   
 /* devices' regs that we will touch in config_machineinit() */  #include <dev/cpuvar.h>
 #include <arch/sam7s64/dev/sapmcreg.h>  #include <arch/sam7s64/dev/at91sam7.h>
 #include <arch/sam7s64/dev/sawdtreg.h>  
 #include <arch/sam7s64/dev/sapioreg.h>  
 #include <arch/sam7s64/dev/sausartreg.h>  
   
 /*  /*
  * Configuration file for platform (AT91SAM7S64).   * Configuration file for platform (AT91SAM7S64).
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 extern struct driver gpioled_dr;  extern struct driver gpioled_dr;
   
   
 extern void(*putchar)(char);  extern void     (*putchar)(char);
 void    sauart_early_putc(char ch);  extern void     sausart_0_putchar(char ch);
   
 /* amount of physical memory, in Bytes */  /* amount of physical memory, in Bytes */
 uint32_t physmem = 16384 /* 16KB :) */;  uint32_t physmem = 16384 /* 16KB :) */;
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         /*          /*
          * Initialize critical devices at startup.           * Initialize critical devices at startup.
          */           */
           __cpu_disable_irq();
   
         /* XXX kill all magic here */  
   
         /* disable watchdog */          /* disable watchdog */
         *(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */;          *AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
   
         /* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */          /* set FLASH to high-speed */
         *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;          *AT91C_MC_FMR = AT91C_MC_FWS_0FWS;
         /* wait main osc. to stabilize.. */  
         while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001)          /*
            * Initialize oscillators.
            * Taken from Atmel's examples.
            */
           /* Set MCK at 48 054 850 */
   
           /* 1 Enabling the Main Oscillator */
       /* SCK = 1/32768 = 30.51 uSecond
        * Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
            */
           *AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN);
   
           /* Wait the startup time */
           while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS))
                 ;                  ;
   
         /* set PLL */          /* 2 Checking the Main Oscillator Frequency (Optional) */
         *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;          /* TODO */
         /* wait.. */  
         while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)          /* 3 Setting PLL and divider: */
           /* - div by 14 Fin = 1.3165 =(18,432 / 14)
            * - Mul 72+1: Fout =   96.1097 =(3,6864 *73)
            * for 96 MHz the erroe is 0.11%
            * Field out NOT USED = 0
            * PLLCOUNT pll startup time estimate at : 0.844 ms
            * PLLCOUNT 28 = 0.000844 /(1/32768)
            */
           *AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 )              |
                                           (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                                           (AT91C_CKGR_MUL & (72<<16)) );
   
           /* Wait the startup time */
           while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK))
                 ;                  ;
         while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)          while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                 ;                  ;
   
         /* select Master Clock and Processor Clock; select (PLL clock / 2) */          /* 4. Selection of Master Clock and Processor Clock */
         *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;          /* select the PLL clock divided by 2: */
         /* wait.. */          *AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2;
         while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)          while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
                 ;                  ;
   
         /*          *AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
          * Enable clock to PIO.          while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))
          */                  ;
         *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */  
   
         /*          /* enable clock to PIO and USART0 */
          * Initialize USART0.          *AT91C_PMC_PCER = AT91C_ID_PIOA | AT91C_ID_US0 AT91C_ID_PDC;
          */  
         /* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */          *AT91C_PIOA_PER = (1 << 17 | 1 << 18);
         *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */          *AT91C_PIOA_OER = (1 << 17 | 1 << 18);
         /* select this pins in Peripheral A */          *AT91C_PIOA_CODR= (1 << 17 | 1 << 18);
         *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */  
   
         /* enable clock to USART0 */          /* initialize USART0 (we clock it in PMC above) */
         *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */  
   
         /* set baud rate */    *AT91C_PIOA_PDR = AT91C_PA5_RXD0 |        /* Enable RxD0 Pin */
         *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */                      AT91C_PA6_TXD0;         /* Enalbe TxD0 Pin */
   
         /* select usart mode */    *AT91C_US0_CR = AT91C_US_RSTRX |          /* Reset Receiver      */
         *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */                    AT91C_US_RSTTX |          /* Reset Transmitter   */
                     AT91C_US_RXDIS |          /* Receiver Disable    */
                     AT91C_US_TXDIS;           /* Transmitter Disable */
   
         /* TODO enable DMA transfers for TX/RX in PDC */    *AT91C_US0_MR = AT91C_US_USMODE_NORMAL |  /* Normal Mode */
                     AT91C_US_CLKS_CLOCK    |  /* Clock = MCK */
                     AT91C_US_CHRL_8_BITS   |  /* 8-bit Data  */
                     AT91C_US_PAR_NONE      |  /* No Parity   */
                     AT91C_US_NBSTOP_1_BIT;    /* 1 Stop Bit  */
   
         /* enable transmitter/receiver */    *AT91C_US0_BRGR = 48054857 / 16 / 9600;                    /* Baud Rate Divisor */
         *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */  
   
         /* TODO redefine putchar */    *AT91C_US0_CR = AT91C_US_RXEN  |          /* Receiver Enable     */
         //putchar = sausart_0_putchar;                    AT91C_US_TXEN;            /* Transmitter Enable  */
   
           /* redefine putchar */
           putchar = sausart_0_putchar;
   //      putchar(0);
   //      putchar(0x46);
   //      putchar(0x46);
 }  }
   
   
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