=================================================================== RCS file: /cvs/funnyos/arch/sam7s64/config.c,v retrieving revision 1.8 retrieving revision 1.9 diff -u -r1.8 -r1.9 --- funnyos/arch/sam7s64/config.c 2007/11/19 10:53:57 1.8 +++ funnyos/arch/sam7s64/config.c 2007/11/24 10:12:44 1.9 @@ -1,14 +1,11 @@ /* - * $Id: config.c,v 1.8 2007/11/19 10:53:57 nbrk Exp $ + * $Id: config.c,v 1.9 2007/11/24 10:12:44 nbrk Exp $ */ #include #include -/* devices' regs that we will touch in config_machineinit() */ -#include -#include -#include -#include +#include +#include /* * Configuration file for platform (AT91SAM7S64). @@ -22,8 +19,8 @@ extern struct driver gpioled_dr; -extern void(*putchar)(char); -void sauart_early_putc(char ch); +extern void (*putchar)(char); +extern void sausart_0_putchar(char ch); /* amount of physical memory, in Bytes */ uint32_t physmem = 16384 /* 16KB :) */; @@ -66,61 +63,94 @@ /* * Initialize critical devices at startup. */ + __cpu_disable_irq(); - /* XXX kill all magic here */ - /* disable watchdog */ - *(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */; + *AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS; - /* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */ - *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701; - /* wait main osc. to stabilize.. */ - while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001) + /* set FLASH to high-speed */ + *AT91C_MC_FMR = AT91C_MC_FWS_0FWS; + + /* + * Initialize oscillators. + * Taken from Atmel's examples. + */ + /* Set MCK at 48 054 850 */ + + /* 1 Enabling the Main Oscillator */ + /* SCK = 1/32768 = 30.51 uSecond + * Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms + */ + *AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN); + + /* Wait the startup time */ + while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS)) ; - /* set PLL */ - *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805; - /* wait.. */ - while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004) + /* 2 Checking the Main Oscillator Frequency (Optional) */ + /* TODO */ + + /* 3 Setting PLL and divider: */ + /* - div by 14 Fin = 1.3165 =(18,432 / 14) + * - Mul 72+1: Fout = 96.1097 =(3,6864 *73) + * for 96 MHz the erroe is 0.11% + * Field out NOT USED = 0 + * PLLCOUNT pll startup time estimate at : 0.844 ms + * PLLCOUNT 28 = 0.000844 /(1/32768) + */ + *AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 ) | + (AT91C_CKGR_PLLCOUNT & (28<<8)) | + (AT91C_CKGR_MUL & (72<<16)) ); + + /* Wait the startup time */ + while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK)) ; - while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */) + while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) ; - /* select Master Clock and Processor Clock; select (PLL clock / 2) */ - *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */; - /* wait.. */ - while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008) + /* 4. Selection of Master Clock and Processor Clock */ + /* select the PLL clock divided by 2: */ + *AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2; + while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) ; - /* - * Enable clock to PIO. - */ - *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */ + *AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; + while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) + ; - /* - * Initialize USART0. - */ - /* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */ - *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */ - /* select this pins in Peripheral A */ - *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */ + /* enable clock to PIO and USART0 */ + *AT91C_PMC_PCER = AT91C_ID_PIOA | AT91C_ID_US0 AT91C_ID_PDC; + + *AT91C_PIOA_PER = (1 << 17 | 1 << 18); + *AT91C_PIOA_OER = (1 << 17 | 1 << 18); + *AT91C_PIOA_CODR= (1 << 17 | 1 << 18); - /* enable clock to USART0 */ - *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */ + /* initialize USART0 (we clock it in PMC above) */ - /* set baud rate */ - *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */ + *AT91C_PIOA_PDR = AT91C_PA5_RXD0 | /* Enable RxD0 Pin */ + AT91C_PA6_TXD0; /* Enalbe TxD0 Pin */ - /* select usart mode */ - *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */ + *AT91C_US0_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ - /* TODO enable DMA transfers for TX/RX in PDC */ + *AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* enable transmitter/receiver */ - *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */ + *AT91C_US0_BRGR = 48054857 / 16 / 9600; /* Baud Rate Divisor */ - /* TODO redefine putchar */ - //putchar = sausart_0_putchar; + *AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ + + /* redefine putchar */ + putchar = sausart_0_putchar; +// putchar(0); +// putchar(0x46); +// putchar(0x46); }