===================================================================
RCS file: /cvs/funnyos/arch/sam7s64/config.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -r1.5 -r1.6
--- funnyos/arch/sam7s64/config.c	2007/11/13 22:40:33	1.5
+++ funnyos/arch/sam7s64/config.c	2007/11/15 20:40:12	1.6
@@ -1,5 +1,5 @@
 /*
- * $Id: config.c,v 1.5 2007/11/13 22:40:33 nbrk Exp $
+ * $Id: config.c,v 1.6 2007/11/15 20:40:12 nbrk Exp $
  */
 #include <sys/types.h>
 #include <sys/device.h>
@@ -63,49 +63,54 @@
 	/* XXX kill all magic here */
 
 	/* disable watchdog */
-	*(uint32_t)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000 /* WDDIS */;
+	*(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */;
 
 	/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */
-	(uint32_t)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;
+	*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;
 	/* wait main osc. to stabilize.. */
-	while (! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001 )
+	while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001)
 		;
 
 	/* set PLL */
-	*(uint32_t)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;
+	*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;
 	/* wait.. */
-	while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)
+	while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)
 		;
-	while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)
+	while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)
 		;
 
 	/* select Master Clock and Processor Clock; select (PLL clock / 2) */
-	*(uint32_t)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;
+	*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;
 	/* wait.. */
-	while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)
+	while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)
 		;
 
 	/*
+	 * Enable clock to PIO.
+	 */
+	*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */
+
+	/*
 	 * Initialize USART0.
 	 */
 	/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */
-	*(uint32_t)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030 /* PIN5 | PIN6 */
+	*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */
 	/* select this pins in Peripheral A */
-	*(uint32_t)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030 /* now, RXD0 | TXD0 */
+	*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */
 
 	/* enable clock to USART0 */
-	*(uint32_t)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006 /* 6 is ID of USART0 */
+	*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */
 
 	/* set baud rate */
-	*(uint32_t)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313 /* XXX (48000000 / 9600 * 16) */
+	*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */
 
 	/* select usart mode */
-	*(uint32_t)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0 /* XXX eleminate magic */
+	*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */
 
 	/* TODO enable DMA transfers for TX/RX in PDC */
 
 	/* enable transmitter/receiver */
-	*(uint32_t)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050 /* TXEN | RXEN */
+	*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */
 
 	/* TODO redefine putchar */
 	//putchar = sausart_0_putchar;