===================================================================
RCS file: /cvs/funnyos/arch/sam7s64/config.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -r1.4 -r1.5
--- funnyos/arch/sam7s64/config.c	2007/11/13 15:41:35	1.4
+++ funnyos/arch/sam7s64/config.c	2007/11/13 22:40:33	1.5
@@ -1,11 +1,14 @@
 /*
- * $Id: config.c,v 1.4 2007/11/13 15:41:35 nbrk Exp $
+ * $Id: config.c,v 1.5 2007/11/13 22:40:33 nbrk Exp $
  */
 #include <sys/types.h>
 #include <sys/device.h>
 
 /* devices' regs that we will touch in config_machineinit() */ 
 #include <arch/sam7s64/dev/sapmcreg.h>
+#include <arch/sam7s64/dev/sawdtreg.h>
+#include <arch/sam7s64/dev/sapioreg.h>
+#include <arch/sam7s64/dev/sausartreg.h>
 
 /*
  * Configuration file for platform (AT91SAM7S64).
@@ -21,7 +24,7 @@
 void 	sauart_early_putc(char ch);
 
 /* amount of physical memory, in Bytes */
-uint32_t physmem = 16384;
+uint32_t physmem = 16384 /* 16KB :) */;
 
 /*
  * Where to attach each device.
@@ -57,17 +60,55 @@
 	 * Initialize critical devices at startup.
 	 */
 
-	/* XXX kill magic */
+	/* XXX kill all magic here */
 
-	/* enable main oscillator and set 6 Slow Clock cycles to wait for its startup */
-	*(uint32_t)(SAPMC_BASE + SAPMC_CKGR_MOR) = (0x0000ff00 & (0x06 << 8)) | 0x00000001;
+	/* disable watchdog */
+	*(uint32_t)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000 /* WDDIS */;
 
+	/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */
+	(uint32_t)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;
 	/* wait main osc. to stabilize.. */
-	while (*(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001 )
+	while (! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001 )
 		;
 
-	/* TODO set PLL */
-//	*(uint32_t)(SAPMC_BASE + SAPMC_PMC_MCKR) = 
+	/* set PLL */
+	*(uint32_t)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;
+	/* wait.. */
+	while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)
+		;
+	while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)
+		;
+
+	/* select Master Clock and Processor Clock; select (PLL clock / 2) */
+	*(uint32_t)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;
+	/* wait.. */
+	while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)
+		;
+
+	/*
+	 * Initialize USART0.
+	 */
+	/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */
+	*(uint32_t)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030 /* PIN5 | PIN6 */
+	/* select this pins in Peripheral A */
+	*(uint32_t)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030 /* now, RXD0 | TXD0 */
+
+	/* enable clock to USART0 */
+	*(uint32_t)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006 /* 6 is ID of USART0 */
+
+	/* set baud rate */
+	*(uint32_t)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313 /* XXX (48000000 / 9600 * 16) */
+
+	/* select usart mode */
+	*(uint32_t)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0 /* XXX eleminate magic */
+
+	/* TODO enable DMA transfers for TX/RX in PDC */
+
+	/* enable transmitter/receiver */
+	*(uint32_t)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050 /* TXEN | RXEN */
+
+	/* TODO redefine putchar */
+	//putchar = sausart_0_putchar;
 }