version 1.4, 2007/11/13 15:41:35 |
version 1.6, 2007/11/15 20:40:12 |
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/* devices' regs that we will touch in config_machineinit() */ |
/* devices' regs that we will touch in config_machineinit() */ |
#include <arch/sam7s64/dev/sapmcreg.h> |
#include <arch/sam7s64/dev/sapmcreg.h> |
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#include <arch/sam7s64/dev/sawdtreg.h> |
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#include <arch/sam7s64/dev/sapioreg.h> |
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#include <arch/sam7s64/dev/sausartreg.h> |
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/* |
/* |
* Configuration file for platform (AT91SAM7S64). |
* Configuration file for platform (AT91SAM7S64). |
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void sauart_early_putc(char ch); |
void sauart_early_putc(char ch); |
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/* amount of physical memory, in Bytes */ |
/* amount of physical memory, in Bytes */ |
uint32_t physmem = 16384; |
uint32_t physmem = 16384 /* 16KB :) */; |
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/* |
/* |
* Where to attach each device. |
* Where to attach each device. |
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* Initialize critical devices at startup. |
* Initialize critical devices at startup. |
*/ |
*/ |
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/* XXX kill magic */ |
/* XXX kill all magic here */ |
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/* enable main oscillator and set 6 Slow Clock cycles to wait for its startup */ |
/* disable watchdog */ |
*(uint32_t)(SAPMC_BASE + SAPMC_CKGR_MOR) = (0x0000ff00 & (0x06 << 8)) | 0x00000001; |
*(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */; |
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/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */ |
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*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701; |
/* wait main osc. to stabilize.. */ |
/* wait main osc. to stabilize.. */ |
while (*(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001 ) |
while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001) |
; |
; |
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/* TODO set PLL */ |
/* set PLL */ |
// *(uint32_t)(SAPMC_BASE + SAPMC_PMC_MCKR) = |
*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805; |
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/* wait.. */ |
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while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004) |
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; |
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while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */) |
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; |
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/* select Master Clock and Processor Clock; select (PLL clock / 2) */ |
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*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */; |
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/* wait.. */ |
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while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008) |
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; |
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/* |
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* Enable clock to PIO. |
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*/ |
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*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */ |
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/* |
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* Initialize USART0. |
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*/ |
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/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */ |
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*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */ |
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/* select this pins in Peripheral A */ |
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*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */ |
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/* enable clock to USART0 */ |
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*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */ |
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/* set baud rate */ |
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*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */ |
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/* select usart mode */ |
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*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */ |
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/* TODO enable DMA transfers for TX/RX in PDC */ |
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/* enable transmitter/receiver */ |
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*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */ |
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/* TODO redefine putchar */ |
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//putchar = sausart_0_putchar; |
} |
} |
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