funnyos/arch/sam7s64/config.c - diff

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Diff for /funnyos/arch/sam7s64/config.c between version 1.3 and 1.6

-version 1.3, 2007/11/09 16:12:15
+version 1.6, 2007/11/15 20:40:12
 Line 4
 Line 4
 Line 4
  #include <sys/types.h>
  #include <sys/device.h>
+ /* devices' regs that we will touch in config_machineinit() */
+ #include <arch/sam7s64/dev/sapmcreg.h>
+ #include <arch/sam7s64/dev/sawdtreg.h>
+ #include <arch/sam7s64/dev/sapioreg.h>
+ #include <arch/sam7s64/dev/sausartreg.h>
  /*
   * Configuration file for platform (AT91SAM7S64).
   */
-Line 18
+Line 24
 Line 18
 Line 24
  void    sauart_early_putc(char ch);
  /* amount of physical memory, in Bytes */
- uint32_t physmem = 16384;
+ uint32_t physmem = 16384 /* 16KB :) */;
  /*
   * Where to attach each device.
-Line 48
+Line 54
 Line 48
 Line 54
   */
  void
- config_consinit(void)
+ config_machineinit(void)
  {
          /*
-          * Configure putchar, so we can printf messages to the console without fcons.
+          * Initialize critical devices at startup.
           */
-         /* putchar = tauart_early_putc; */
+         /* XXX kill all magic here */
+         /* disable watchdog */
+         *(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */;
+         /* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */
+         *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;
+         /* wait main osc. to stabilize.. */
+         while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001)
+                 ;
+         /* set PLL */
+         *(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;
+         /* wait.. */
+         while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)
+                 ;
+         while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)
+                 ;
+         /* select Master Clock and Processor Clock; select (PLL clock / 2) */
+         *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;
+         /* wait.. */
+         while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)
+                 ;
+         /*
+          * Enable clock to PIO.
+          */
+         *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */
+         /*
+          * Initialize USART0.
+          */
+         /* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */
+         *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */
+         /* select this pins in Peripheral A */
+         *(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */
+         /* enable clock to USART0 */
+         *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */
+         /* set baud rate */
+         *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */
+         /* select usart mode */
+         *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */
+         /* TODO enable DMA transfers for TX/RX in PDC */
+         /* enable transmitter/receiver */
+         *(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */
+         /* TODO redefine putchar */
+         //putchar = sausart_0_putchar;
  }

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