version 1.5, 2007/11/13 22:40:33 |
version 1.6, 2007/11/15 20:40:12 |
|
|
/* XXX kill all magic here */ |
/* XXX kill all magic here */ |
|
|
/* disable watchdog */ |
/* disable watchdog */ |
*(uint32_t)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000 /* WDDIS */; |
*(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */; |
|
|
/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */ |
/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */ |
(uint32_t)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701; |
*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701; |
/* wait main osc. to stabilize.. */ |
/* wait main osc. to stabilize.. */ |
while (! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001 ) |
while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001) |
; |
; |
|
|
/* set PLL */ |
/* set PLL */ |
*(uint32_t)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805; |
*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805; |
/* wait.. */ |
/* wait.. */ |
while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004) |
while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004) |
; |
; |
while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */) |
while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */) |
; |
; |
|
|
/* select Master Clock and Processor Clock; select (PLL clock / 2) */ |
/* select Master Clock and Processor Clock; select (PLL clock / 2) */ |
*(uint32_t)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */; |
*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */; |
/* wait.. */ |
/* wait.. */ |
while(! *(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008) |
while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008) |
; |
; |
|
|
/* |
/* |
|
* Enable clock to PIO. |
|
*/ |
|
*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */ |
|
|
|
/* |
* Initialize USART0. |
* Initialize USART0. |
*/ |
*/ |
/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */ |
/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */ |
*(uint32_t)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030 /* PIN5 | PIN6 */ |
*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */ |
/* select this pins in Peripheral A */ |
/* select this pins in Peripheral A */ |
*(uint32_t)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030 /* now, RXD0 | TXD0 */ |
*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */ |
|
|
/* enable clock to USART0 */ |
/* enable clock to USART0 */ |
*(uint32_t)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006 /* 6 is ID of USART0 */ |
*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */ |
|
|
/* set baud rate */ |
/* set baud rate */ |
*(uint32_t)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313 /* XXX (48000000 / 9600 * 16) */ |
*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */ |
|
|
/* select usart mode */ |
/* select usart mode */ |
*(uint32_t)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0 /* XXX eleminate magic */ |
*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */ |
|
|
/* TODO enable DMA transfers for TX/RX in PDC */ |
/* TODO enable DMA transfers for TX/RX in PDC */ |
|
|
/* enable transmitter/receiver */ |
/* enable transmitter/receiver */ |
*(uint32_t)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050 /* TXEN | RXEN */ |
*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */ |
|
|
/* TODO redefine putchar */ |
/* TODO redefine putchar */ |
//putchar = sausart_0_putchar; |
//putchar = sausart_0_putchar; |