version 1.4, 2007/11/13 15:41:35 |
version 1.12, 2007/11/24 17:45:19 |
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#include <sys/types.h> |
#include <sys/types.h> |
#include <sys/device.h> |
#include <sys/device.h> |
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/* devices' regs that we will touch in config_machineinit() */ |
#include <dev/cpuvar.h> |
#include <arch/sam7s64/dev/sapmcreg.h> |
#include <arch/sam7s64/dev/at91sam7.h> |
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/* |
/* |
* Configuration file for platform (AT91SAM7S64). |
* Configuration file for platform (AT91SAM7S64). |
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extern struct driver root_dr; |
extern struct driver root_dr; |
extern struct driver cpu_dr; |
extern struct driver cpu_dr; |
extern struct driver saapbus_dr; |
extern struct driver saapbus_dr; |
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extern struct driver sapio_dr; |
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extern struct driver gpioled_dr; |
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extern void(*putchar)(char); |
extern void (*putchar)(char); |
void sauart_early_putc(char ch); |
extern void sausart_early_putchar(char ch); |
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/* amount of physical memory, in Bytes */ |
/* amount of physical memory, in Bytes */ |
uint32_t physmem = 16384; |
uint32_t physmem = 16384 /* 16KB :) */; |
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/* |
/* |
* Where to attach each device. |
* Where to attach each device. |
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/* child, parent, pminor, loc, intrno, flags */ |
/* child, parent, pminor, loc, intrno, flags */ |
{ "cpu" , "root", 0, 0, 0, 0 }, |
{ "cpu" , "root", 0, 0, 0, 0 }, |
{ "saapbus","root", 0, 0, 0, 0 }, |
{ "saapbus","root", 0, 0, 0, 0 }, |
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{ "sapio", "saapbus", 0, 0, 0, 0 }, |
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{ "gpioled","sapio", 0, 17, 0, 0 }, |
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{ "gpioled","sapio", 0, 18, 0, 0 }, |
{ NULL, NULL, 0, 0, 0, 0 } |
{ NULL, NULL, 0, 0, 0, 0 } |
}; |
}; |
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{ "root", &root_dr, -1 }, |
{ "root", &root_dr, -1 }, |
{ "cpu" , &cpu_dr, -1 }, |
{ "cpu" , &cpu_dr, -1 }, |
{ "saapbus" , &saapbus_dr, -1 }, |
{ "saapbus" , &saapbus_dr, -1 }, |
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{ "sapio", &sapio_dr, -1 }, |
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{ "gpioled", &gpioled_dr, -1 }, |
{ NULL, NULL, 0 } |
{ NULL, NULL, 0 } |
}; |
}; |
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/* |
/* |
* Initialize critical devices at startup. |
* Initialize critical devices at startup. |
*/ |
*/ |
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__cpu_disable_irq(); |
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/* XXX kill magic */ |
/* disable watchdog */ |
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*AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS; |
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/* enable main oscillator and set 6 Slow Clock cycles to wait for its startup */ |
/* set FLASH to high-speed */ |
*(uint32_t)(SAPMC_BASE + SAPMC_CKGR_MOR) = (0x0000ff00 & (0x06 << 8)) | 0x00000001; |
*AT91C_MC_FMR = AT91C_MC_FWS_0FWS; |
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/* wait main osc. to stabilize.. */ |
/* enable user RESET (magic button on board) */ |
while (*(uint32_t)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001 ) |
*AT91C_RSTC_RMR = AT91C_RSTC_URSTEN | AT91C_RSTC_KEY; |
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/* |
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* Initialize oscillators. |
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* Taken from Atmel's examples. |
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*/ |
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/* Set MCK at 48 054 850 */ |
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/* 1 Enabling the Main Oscillator */ |
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/* SCK = 1/32768 = 30.51 uSecond |
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* Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms |
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*/ |
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*AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN); |
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/* Wait the startup time */ |
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while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS)) |
; |
; |
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/* TODO set PLL */ |
/* 2 Checking the Main Oscillator Frequency (Optional) */ |
// *(uint32_t)(SAPMC_BASE + SAPMC_PMC_MCKR) = |
/* TODO */ |
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/* 3 Setting PLL and divider: */ |
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/* - div by 14 Fin = 1.3165 =(18,432 / 14) |
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* - Mul 72+1: Fout = 96.1097 =(3,6864 *73) |
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* for 96 MHz the erroe is 0.11% |
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* Field out NOT USED = 0 |
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* PLLCOUNT pll startup time estimate at : 0.844 ms |
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* PLLCOUNT 28 = 0.000844 /(1/32768) |
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*/ |
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*AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 ) | |
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(AT91C_CKGR_PLLCOUNT & (28<<8)) | |
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(AT91C_CKGR_MUL & (72<<16)) ); |
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/* Wait the startup time */ |
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while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK)) |
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; |
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while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) |
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; |
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/* 4. Selection of Master Clock and Processor Clock */ |
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/* select the PLL clock divided by 2: */ |
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*AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2; |
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while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) |
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; |
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*AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; |
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while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) |
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; |
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/* enable clock to all modules */ |
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*AT91C_PMC_PCER = AT91C_ALL_INT; |
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/* initialize USART0 (we clock it in PMC above) */ |
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*AT91C_PIOA_PDR = AT91C_PA5_RXD0 | /* Enable RxD0 Pin */ |
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AT91C_PA6_TXD0; /* Enalbe TxD0 Pin */ |
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*AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ |
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AT91C_US_CLKS_CLOCK | /* Clock = MCK */ |
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AT91C_US_CHRL_8_BITS | /* 8-bit Data */ |
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AT91C_US_PAR_NONE | /* No Parity */ |
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AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ |
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*AT91C_US0_BRGR = 48054857 / 16 / 9600; /* Baud Rate Divisor */ |
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/* enable DMA transfers on USART0 */ |
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*AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN; |
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*AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */ |
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AT91C_US_TXEN; /* Transmitter Enable */ |
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/* redefine putchar */ |
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putchar = sausart_early_putchar; |
} |
} |
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