funnyos/arch/sam7s64/config.c - diff

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Diff for /funnyos/arch/sam7s64/config.c between version 1.8 and 1.13

version 1.8, 2007/11/19 10:53:57

version 1.13, 2007/11/24 20:52:29

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#include <sys/types.h>

#include <sys/device.h>

/* devices' regs that we will touch in config_machineinit() */

#include <dev/cpuvar.h>

#include <arch/sam7s64/dev/sapmcreg.h>

#include <arch/sam7s64/dev/at91sam7.h>

#include <arch/sam7s64/dev/sawdtreg.h>

#include <arch/sam7s64/dev/sapioreg.h>

#include <arch/sam7s64/dev/sausartreg.h>

* Configuration file for platform (AT91SAM7S64).

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extern struct driver saapbus_dr;

extern struct driver sapio_dr;

extern struct driver gpioled_dr;

extern struct driver saaic_dr;

extern struct driver sartt_dr;

extern void(*putchar)(char);

extern void (*putchar)(char);

void sauart_early_putc(char ch);

extern void sausart_early_putchar(char ch);

/* amount of physical memory, in Bytes */

uint32_t physmem = 16384 /* 16KB :) */;

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{ "sapio", "saapbus", 0, 0, 0, 0 },

{ "gpioled","sapio", 0, 17, 0, 0 },

{ "gpioled","sapio", 0, 18, 0, 0 },

{ "sartt", "saapbus", 0, 0, 1, 0 },

{ "saaic", "saapbus", 0, 0, 0, 0 },

{ NULL, NULL, 0, 0, 0, 0 }

};

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{ "saapbus" , &saapbus_dr, -1 },

{ "sapio", &sapio_dr, -1 },

{ "gpioled", &gpioled_dr, -1 },

{ "saaic", &saaic_dr, -1 },

{ "sartt", &sartt_dr, -1 },

{ NULL, NULL, 0 }

};

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* Initialize critical devices at startup.

__cpu_disable_irq();

/* XXX kill all magic here */

/* disable watchdog */

*(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */;

*AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;

/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */

/* set FLASH to high-speed */

*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701;

*AT91C_MC_FMR = AT91C_MC_FWS_0FWS;

/* wait main osc. to stabilize.. */

while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001)

/* enable user RESET (magic button on board) */

*AT91C_RSTC_RMR = AT91C_RSTC_URSTEN | AT91C_RSTC_KEY;

* Initialize oscillators.

* Taken from Atmel's examples.

/* Set MCK at 48 054 850 */

/* 1 Enabling the Main Oscillator */

/* SCK = 1/32768 = 30.51 uSecond

* Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms

*AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN);

/* Wait the startup time */

while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS))

;

/* set PLL */

/* 2 Checking the Main Oscillator Frequency (Optional) */

*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805;

/* TODO */

/* wait.. */

while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004)

/* 3 Setting PLL and divider: */

/* - div by 14 Fin = 1.3165 =(18,432 / 14)

* - Mul 72+1: Fout = 96.1097 =(3,6864 *73)

* for 96 MHz the erroe is 0.11%

* Field out NOT USED = 0

* PLLCOUNT pll startup time estimate at : 0.844 ms

* PLLCOUNT 28 = 0.000844 /(1/32768)

*AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 ) |

(AT91C_CKGR_PLLCOUNT & (28<<8)) |

(AT91C_CKGR_MUL & (72<<16)) );

/* Wait the startup time */

while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK))

;

while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */)

while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))

;

/* select Master Clock and Processor Clock; select (PLL clock / 2) */

/* 4. Selection of Master Clock and Processor Clock */

*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */;

/* select the PLL clock divided by 2: */

/* wait.. */

*AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2;

while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008)

while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))

;

*AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;

* Enable clock to PIO.

while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY))

;

*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */

/* enable clock to all modules */

* Initialize USART0.

*AT91C_PMC_PCER = AT91C_ALL_INT;

/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */

/* initialize USART0 (we clock it in PMC above) */

*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */

/* select this pins in Peripheral A */

*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */

/* enable clock to USART0 */

*AT91C_PIOA_PDR = AT91C_PA5_RXD0 | /* Enable RxD0 Pin */

*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */

AT91C_PA6_TXD0; /* Enalbe TxD0 Pin */

/* set baud rate */

*AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */

*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */

AT91C_US_CLKS_CLOCK | /* Clock = MCK */

AT91C_US_CHRL_8_BITS | /* 8-bit Data */

AT91C_US_PAR_NONE | /* No Parity */

AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */

/* select usart mode */

*AT91C_US0_BRGR = 48054857 / 16 / 9600; /* Baud Rate Divisor */

*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */

/* TODO enable DMA transfers for TX/RX in PDC */

/* enable DMA transfers on USART0 */

*AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN;

/* enable transmitter/receiver */

*AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */

*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */

AT91C_US_TXEN; /* Transmitter Enable */

/* TODO redefine putchar */

/* redefine putchar */

//putchar = sausart_0_putchar;

putchar = sausart_early_putchar;

}

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