version 1.8, 2007/11/19 10:53:57 |
version 1.12, 2007/11/24 17:45:19 |
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#include <sys/types.h> |
#include <sys/types.h> |
#include <sys/device.h> |
#include <sys/device.h> |
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/* devices' regs that we will touch in config_machineinit() */ |
#include <dev/cpuvar.h> |
#include <arch/sam7s64/dev/sapmcreg.h> |
#include <arch/sam7s64/dev/at91sam7.h> |
#include <arch/sam7s64/dev/sawdtreg.h> |
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#include <arch/sam7s64/dev/sapioreg.h> |
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#include <arch/sam7s64/dev/sausartreg.h> |
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/* |
/* |
* Configuration file for platform (AT91SAM7S64). |
* Configuration file for platform (AT91SAM7S64). |
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extern struct driver gpioled_dr; |
extern struct driver gpioled_dr; |
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extern void(*putchar)(char); |
extern void (*putchar)(char); |
void sauart_early_putc(char ch); |
extern void sausart_early_putchar(char ch); |
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/* amount of physical memory, in Bytes */ |
/* amount of physical memory, in Bytes */ |
uint32_t physmem = 16384 /* 16KB :) */; |
uint32_t physmem = 16384 /* 16KB :) */; |
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/* |
/* |
* Initialize critical devices at startup. |
* Initialize critical devices at startup. |
*/ |
*/ |
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__cpu_disable_irq(); |
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/* XXX kill all magic here */ |
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/* disable watchdog */ |
/* disable watchdog */ |
*(uint32_t *)(SAWDT_BASE + SAWDT_WDT_MR) |= 0x00001000; /* WDDIS */; |
*AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS; |
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/* "Start up time = 8 * OSCOUNT / SLCK" (slow clock cycles) */ |
/* set FLASH to high-speed */ |
*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_MOR) = 0x00000701; |
*AT91C_MC_FMR = AT91C_MC_FWS_0FWS; |
/* wait main osc. to stabilize.. */ |
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while (! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000001) |
/* enable user RESET (magic button on board) */ |
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*AT91C_RSTC_RMR = AT91C_RSTC_URSTEN | AT91C_RSTC_KEY; |
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/* |
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* Initialize oscillators. |
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* Taken from Atmel's examples. |
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*/ |
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/* Set MCK at 48 054 850 */ |
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/* 1 Enabling the Main Oscillator */ |
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/* SCK = 1/32768 = 30.51 uSecond |
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* Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms |
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*/ |
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*AT91C_PMC_MOR = ( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN); |
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/* Wait the startup time */ |
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while(!(*AT91C_PMC_SR & AT91C_PMC_MOSCS)) |
; |
; |
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/* set PLL */ |
/* 2 Checking the Main Oscillator Frequency (Optional) */ |
*(uint32_t *)(SAPMC_BASE + SAPMC_CKGR_PLLR) = 0x00040805; |
/* TODO */ |
/* wait.. */ |
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while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000004) |
/* 3 Setting PLL and divider: */ |
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/* - div by 14 Fin = 1.3165 =(18,432 / 14) |
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* - Mul 72+1: Fout = 96.1097 =(3,6864 *73) |
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* for 96 MHz the erroe is 0.11% |
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* Field out NOT USED = 0 |
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* PLLCOUNT pll startup time estimate at : 0.844 ms |
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* PLLCOUNT 28 = 0.000844 /(1/32768) |
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*/ |
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*AT91C_PMC_PLLR = ( (AT91C_CKGR_DIV & 14 ) | |
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(AT91C_CKGR_PLLCOUNT & (28<<8)) | |
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(AT91C_CKGR_MUL & (72<<16)) ); |
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/* Wait the startup time */ |
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while(!(*AT91C_PMC_SR & AT91C_PMC_LOCK)) |
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; |
while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008 /* MCKRDY */) |
while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) |
; |
; |
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/* select Master Clock and Processor Clock; select (PLL clock / 2) */ |
/* 4. Selection of Master Clock and Processor Clock */ |
*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_MCKR) = 0x00000003 /* PLL in CSS */ | 0x00000004 /* presc. = 2 */; |
/* select the PLL clock divided by 2: */ |
/* wait.. */ |
*AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2; |
while(! *(uint32_t *)(SAPMC_BASE + SAPMC_PMC_SR) & 0x00000008) |
while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) |
; |
; |
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/* |
*AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; |
* Enable clock to PIO. |
while(!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)) |
*/ |
; |
*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000002; /* 2 is ID of PIOA */ |
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/* |
/* enable clock to all modules */ |
* Initialize USART0. |
*AT91C_PMC_PCER = AT91C_ALL_INT; |
*/ |
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/* disable PIO from controlling RXD0/TXD0 pins (USART0 at Periph. A) */ |
/* initialize USART0 (we clock it in PMC above) */ |
*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_PDR) = 0x00000030; /* PIN5 | PIN6 */ |
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/* select this pins in Peripheral A */ |
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*(uint32_t *)(SAPIO_BASE + SAPIO_PIO_ASR) = 0x00000030; /* now, RXD0 | TXD0 */ |
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/* enable clock to USART0 */ |
*AT91C_PIOA_PDR = AT91C_PA5_RXD0 | /* Enable RxD0 Pin */ |
*(uint32_t *)(SAPMC_BASE + SAPMC_PMC_PCER) = 0x00000006; /* 6 is ID of USART0 */ |
AT91C_PA6_TXD0; /* Enalbe TxD0 Pin */ |
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/* set baud rate */ |
*AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ |
*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_BRGR) = 313; /* XXX (48000000 / 9600 * 16) */ |
AT91C_US_CLKS_CLOCK | /* Clock = MCK */ |
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AT91C_US_CHRL_8_BITS | /* 8-bit Data */ |
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AT91C_US_PAR_NONE | /* No Parity */ |
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AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ |
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/* select usart mode */ |
*AT91C_US0_BRGR = 48054857 / 16 / 9600; /* Baud Rate Divisor */ |
*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_MR) = 0x000008c0; /* XXX eleminate magic */ |
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/* TODO enable DMA transfers for TX/RX in PDC */ |
/* enable DMA transfers on USART0 */ |
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*AT91C_US0_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN; |
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/* enable transmitter/receiver */ |
*AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */ |
*(uint32_t *)(SAUSART_0_BASE + SAUSART_US_CR) = 0x00000050; /* TXEN | RXEN */ |
AT91C_US_TXEN; /* Transmitter Enable */ |
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/* TODO redefine putchar */ |
/* redefine putchar */ |
//putchar = sausart_0_putchar; |
putchar = sausart_early_putchar; |
} |
} |
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